Longest-path selection for delay test under process variation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 12, 2005, Pages 1924-1929

  Lu, Xiang ^a   Li, Zhuo ^a   Qiu, Wangqi ^a   Walker, D M H ^a   Shi, Weiping ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Delay test; Interconnect; Optimization; Timing analysis

Indexed keywords

DEFECTS; ELECTRIC POWER SYSTEM INTERCONNECTION; ELECTRONIC EQUIPMENT MANUFACTURE; OPTIMIZATION; PROBLEM SOLVING;

DELAY TEST; INTERCONNECT; LOCAL DEFECTS; TIMING ANALYSIS;

DELAY CIRCUITS;

EID: 29144439093     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.852674     Document Type: Conference Paper

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