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Volumn , Issue , 1996, Pages 117-120

Reliable Tantalum Gate Fully-Depleted-SO1MOSFET’s with 0.15pm Gate Length by Low-Temperature Processing below 500°C

Author keywords

[No Author keywords available]

Indexed keywords

MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY; TANTALUM; CRYSTALLIZATION; GATES (TRANSISTOR); LEAKAGE CURRENTS; LOW TEMPERATURE OPERATIONS; OXIDATION; OXIDES; PRODUCT DESIGN; RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; SPUTTER DEPOSITION;

EID: 0030402063     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.553135     Document Type: Conference Paper
Times cited : (11)

References (11)
  • 2
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    • Threshold voltage adjustment in SO1 MOSFET’s by employing tantalum for gate material
    • H. Shimada, Y. Hirano, T. Ushiki, and T. Ohmi, “Threshold Voltage Adjustment in SO1 MOSFET’s by Employing Tantalum for Gate Material,” Tech.Dig. of IEDM, pp. 881-884, 1995.
    • (1995) Tech.Dig. of IEDM , pp. 881-884
    • Shimada, H.1    Hirano, Y.2    Ushiki, T.3    Ohmi, T.4
  • 3
    • 0029518505 scopus 로고
    • Tantalum-gate SO1 MOSFET’s featuring threshold voltage control in low-power applications
    • Tucson, AZ
    • H. Shimada, T. Ushiki, Y. Hirano, and T. Ohmi, “Tantalum-gate SO1 MOSFET’s featuring threshold voltage control in low-power applications,” 1998 IEEE International SOI Conference Proceedings, pp. 96-97, Tucson, AZ, 1995.
    • (1995) 1998 IEEE International SOI Conference Proceedings , pp. 96-97
    • Shimada, H.1    Ushiki, T.2    Hirano, Y.3    Ohmi, T.4
  • 5
    • 0028746226 scopus 로고
    • Tradeoffs of current drive vs. Short-channel effect in deepsubmicrometer bulk and SO1 MOSFET’s
    • L. T. Su, H. Hu, J. B. Jacobs, M. J. Sherony, A. Wei, and D. A. Antoniadis, “Tradeoffs of current drive vs. short-channel effect in deepsubmicrometer bulk and SO1 MOSFET’s,” Tech. Dig. of IEDM, pp. 649-652, 1994.
    • (1994) Tech. Dig. of IEDM , pp. 649-652
    • Su, L.T.1    Hu, H.2    Jacobs, J.B.3    Sherony, M.J.4    Wei, A.5    Antoniadis, D.A.6
  • 7
    • 0029547927 scopus 로고
    • The effect of sourcedrain processing on the reverse short channel effect of deep sub-micro bulk and SO1 nMOSFETs
    • S. W. Crowder, P. M. Rousseau, J. P. Snyder, J. A. Scott, P. B. Griffin, and J. D. Plummer, “The Effect of SourceDrain Processing on the Reverse Short Channel Effect of Deep Sub-Micro Bulk and SO1 NMOSFETs,” Tech. Dig. of IEDM, pp. 427-430, 1995.
    • (1995) Tech. Dig. of IEDM , pp. 427-430
    • Crowder, S.W.1    Rousseau, P.M.2    Snyder, J.P.3    Scott, J.A.4    Griffin, P.B.5    Plummer, J.D.6
  • 8
    • 0029305379 scopus 로고
    • Eliminating metal-sputter contamination in ion implanter for low-temperature-annealed, low-reverse-bias-curnt junction
    • K. Tomita, T. Migita, S. Shimonishi, T. Shihata, T. Ohmi, and T. Nitta, “Eliminating metal-sputter contamination in ion implanter for low-temperature-annealed, low-reverse-bias-curnt junction,” L Electrochem. Soc., vol. 142, No. 5, pp. 1692-1698, 1995.
    • (1995) L Electrochem. Soc. , vol.142 , Issue.5 , pp. 1692-1698
    • Tomita, K.1    Migita, T.2    Shimonishi, S.3    Shihata, T.4    Ohmi, T.5    Nitta, T.6
  • 9
    • 0024629437 scopus 로고
    • Two-dimensional simulation and measurement of high-performance MOSFET’s made on a very thin SO1 film
    • M. Yoshimi, H. Hazama, M. Takahashi, S. Kambayashi, T. Wada, K. Kato, and H. Tango, “Two-Dimensional Simulation and Measurement of High-Performance MOSFET’s Made on a Very Thin SO1 Film,’’ IEEE Trans. on Electron Devices, Vol. 36, No. 3, pp. 493-503, 1989.
    • (1989) IEEE Trans. on Electron Devices , vol.36 , Issue.3 , pp. 493-503
    • Yoshimi, M.1    Hazama, H.2    Takahashi, M.3    Kambayashi, S.4    Wada, T.5    Kato, K.6    Tango, H.7
  • 10
    • 0028499440 scopus 로고
    • Deep-Suhmicrometer Channel Design in Silicon-on-insulator (SOI) MOSFET’s
    • L. T. Su, J. B. Jacobs, J. E. Chung, and D. A. Antoniadis, “Deep-Suhmicrometer Channel Design in Silicon-on-insulator (SOI) MOSFET’s,” IEEE Electron Device Letters, Vol. 15, No. 9, pp. 366-369, 1994.
    • (1994) IEEE Electron Device Letters , vol.15 , Issue.9 , pp. 366-369
    • Su, L.T.1    Jacobs, J.B.2    Chung, J.E.3    Antoniadis, D.A.4
  • 11
    • 33746189368 scopus 로고
    • 0.1-pm-gate, ultrathin-film CMOS devices using SiMox substrate with 80-nm-thick buried oxide layer
    • Y. Omura, S. Nakanima, K. Izumi, and T. Ishii, “0.1-pm-Gate, Ultrathin-Film CMOS Devices Using SIMOX Substrate with 80-nm-Thick Buried Oxide Layer,” Tech. Dig. ofIEDM, pp. 675-678, 1991.
    • (1991) Tech. Dig. ofIEDM , pp. 675-678
    • Omura, Y.1    Nakanima, S.2    Izumi, K.3    Ishii, T.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.