Improvement of SOI MOS current-mirror performances using serial-parallel association of transistors

Electronics Letters

Volumn 32, Issue 4, 1996, Pages 278-279

  De Ceuster, D ^a,c   Flandre, D ^a   Colinge, J P ^a   Cristoloveanu, S ^b  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^b Grenoble INP Phelma   (France)

^c SunPower Corporation   (United States)

Author keywords

Analogue circuits; MOSFET; Silicon on insulator

Indexed keywords

ELECTRIC BREAKDOWN; ELECTRIC IMPEDANCE; LINEAR INTEGRATED CIRCUITS; MOSFET DEVICES; PERFORMANCE;

ANALOG CIRCUITS; SERIAL PARALLEL COMBINATION;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0030081408     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19960252     Document Type: Article

References (5)

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2. GAO, M.H., COLINGE, J.P., LAUWERS, L., WU, S., and CLAEYS, C.: 'Twin MOSFET structures for suppression of kink and parasitic bipolar effects in SOI MOSFETs at room and liquid helium temperatures', Solid-State Electron., 1992, 35, (4), pp. 505-512
3. DE CEUSTER, D., and FLANDRE, E.: 'Kink-like effect in long n-channel twin-gate fully depleted SOI MOSFETs', Electron. Lett., 1994, 30, (17), pp. 1456-1458
4. GALUP-MONTORO, C., SCHNEIDER, M.C., and LOSS, I.J.B.: 'Series-parallel association of FETs for high-gain and high-frequency applications', IEEE J. Solid-State Electron., 1994, 29, (9), pp. 1094-1101
5. SCHOBER, R.C., et al.: 'Ultra low power techniques for focal plane electronics applications'. JPL Task Plan 80.3293, July 22, 1993