Device and architecture co-optimization for FPGA power reduction

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 915-920

  Cheng, Lerong ^a   Wong, Phoebe ^a   Li, Fei ^a   Lin, Yan ^a   He, Lei ^a  

^a University of California   (United States)

Author keywords

FPGA; Low power; Power gating; Psim; Ptrace

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ELECTRIC POWER SYSTEMS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; OPTIMIZATION;

LOW POWER; POWER-GATING; PSIM; PTRACE;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 27944462311     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1065579.1065819     Document Type: Conference Paper

References (12)

1. J. Rose, R. J. Francis, D. Lewis, and P. Chow, "Architecture of field-programmable gate arrays: The effect of logic functionality on area efficiency," Proc. IEEE Int. Solid-State Circuits Conf., 1990.
2. J. Kouloheris and A. E. Gamal, "FPGA area vs. cell granularity - lookup tables and PLA cells," in 1st ACM Workshop on FPGAs, berkeley, CA, Feb 1992.
3. E. Ahmed and J. Rose, "The effect of LUT and cluster size on deep-submicron FPGA performance and density," in Proc. ACM Intl. Symp. Field-Programmable Gate Arrays, pp. 3-12, Feb 2000.
4. F. Li, D. Chen, L. He, and J. Cong, "Architecture evaluation for power-efficient FPGAs," in Proc. ACM Intl. Symp. Field-Programmable Gate Arrays, Feb 2003.
5. K. Poon, A. Yan, and S. Wilton, "A flexible power model for FPGAs," in Proc. of 18th International conference on Field-Programmable Logic and Applications, Sep 2002.
6. A. Gayasen, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and T. Tuan, "Reducing leakage energy in FPGAs using region-constrained placement," in Proc. ACM Intl. Symp. Field-Programmable Gate Arrays, February 2004.
7. F. Li, Y. Lin, L. He, and J. Cong, "Low-power FPGA using pre-defined dual-vdd/dual-vt fabrics," in Proc. ACM Intl. Symp. Field-Programmable Gate Arrays, February 2004.
8. F. Li, Y. Lin, and L. He, "FPGA power reduction using configurable dual-vdd," in Proc. Design Automation Conf., June 2004.
9. Fei Li, Yan Lin and Lei He, "Vdd programmability to reduce fpga interconnect power," in Proc. Intl. Conf. Computer-Aided Design, November 2004.
10. Y. Lin, F. Li and L. He, "Circuits and architectures for vdd programmable FPGAs," in Proc. ACM Intl. Symp. Field-Programmable Gate Arrays, Feb 2005.
11. International Technology Roadmap for Semiconductor in http://public.itrs.net/, 2002.
12. L. Cheng, P. Wong, F. Li, Y. Lin, and L. He, "Device and architecture co-optimization for FPGA power reduction," Tech. Rep. 05-258, UCLA Engr.