BDD decomposition for delay oriented pass transistor logic synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 8, 2005, Pages 957-970

  Shelar, Rupesh S ^a,b,c   Sapatnekar, Sachin S ^a,b  

^a IEEE   (United States)

^b University of Minnesota   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Binary decision diagrams (BDDs); Functional decomposition; Logic synthesis; Pass transistor logic

Indexed keywords

BINARY DECISION DIAGRAMS (BDD); FUNCTIONAL DECOMPOSITION; LOGIC SYNTHESIS; PASS TRANSISTOR LOGIC;

ALGORITHMS; BENCHMARKING; CMOS INTEGRATED CIRCUITS; DECISION THEORY; LOGIC GATES; NAND CIRCUITS;

TRANSISTORS;

EID: 27144518279     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.853601     Document Type: Article

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