Unified theory to build cell-level transistor networks from BDDs [logic synthesis]

Proceedings - 16th Symposium on Integrated Circuits and Systems Design, SBCCI 2003

Volumn , Issue , 2003, Pages 199-204

  Poli, R E B ^a   Schneider, F R ^a   Ribas, R P ^a   Reis, A I ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

Boolean functions; Circuit synthesis; Circuit topology; CMOS logic circuits; Data structures; Delay; Logic circuits; Network synthesis; Network topology; Very large scale integration

Indexed keywords

BINARY DECISION DIAGRAMS; BOOLEAN FUNCTIONS; DATA STRUCTURES; DECISION THEORY; DELAY CIRCUITS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUITS; LOGIC SYNTHESIS; NETWORKS (CIRCUITS); SYNTHESIS (CHEMICAL); SYSTEMS ANALYSIS; TOPOLOGY; TRANSISTORS; VLSI CIRCUITS;

CIRCUIT SYNTHESIS; CMOS LOGIC CIRCUITS; DELAY; NETWORK SYNTHESIS; NETWORK TOPOLOGY;

LOGIC CIRCUITS;

EID: 33750925327     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2003.1232829     Document Type: Conference Paper

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