Systematic technique for verifying critical path delays in a 300 MHz Alpha CPU design using circuit simulation

Proceedings - Design Automation Conference

Volumn , Issue , 1996, Pages 125-130

  Desai, Madhav P ^a   Yen, Y T ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; EQUIVALENT CIRCUITS; INTEGRATED CIRCUIT LAYOUT; VLSI CIRCUITS;

CENTRAL PROCESSING UNITS (CPU); CIRCUIT SIMULATION; CRITICAL PATH DELAYS; SOFTWARE PACKAGE SPICE;

MICROPROCESSOR CHIPS;

EID: 0029708442     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)