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Volumn 3553, Issue , 2005, Pages 93-102

Flux caches: What are they and are they useful?

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; EMBEDDED SYSTEMS; FLUXES;

EID: 26444481956     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/11512622_11     Document Type: Conference Paper
Times cited : (1)

References (23)
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    • Jouppi, N.P.1
  • 4
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    • Column-associative caches: A technique for reducing the miss rate of direct-mapped caches
    • Agarwal, A., Pudar, S.D.: Column-associative caches: A technique for reducing the miss rate of direct-mapped caches. In: ISCA. (1993) 179-190
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    • A case for two-way skewed-associative caches
    • Seznec, A.: A case for two-way skewed-associative caches. In: ISCA. (1993) 169-178
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    • Seznec, A.1
  • 9
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    • Reconfigurable caches and their application to media processing
    • Ranganathan, P., Adve, S.V., Jouppi, N.P.: Reconfigurable caches and their application to media processing. In: ISCA. (2000) 214-224
    • (2000) ISCA , pp. 214-224
    • Ranganathan, P.1    Adve, S.V.2    Jouppi, N.P.3
  • 10
    • 84942058694 scopus 로고    scopus 로고
    • Energy benefits of a configurable line size cache for embedded systems
    • Zhang, C., Vahid, F., Najjar, W.A.: Energy benefits of a configurable line size cache for embedded systems. In: ISVLSI. (2003) 87-91
    • (2003) ISVLSI , pp. 87-91
    • Zhang, C.1    Vahid, F.2    Najjar, W.A.3
  • 12
    • 26444531754 scopus 로고    scopus 로고
    • Reprogramable Instruction Set Accelerator. U.S. Patent No. 5,737,631
    • Trimberger, S.M.: Reprogramable Instruction Set Accelerator. U.S. Patent No. 5,737,631 (1998)
    • (1998)
    • Trimberger, S.M.1
  • 14
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    • Automatic tuning of two-level caches to embedded applications
    • Gordon-Ross, A., Vahid, F., Dutt, N.: Automatic tuning of two-level caches to embedded applications. In: DATE. (2004) 208-213
    • (2004) DATE , pp. 208-213
    • Gordon-Ross, A.1    Vahid, F.2    Dutt, N.3
  • 17
    • 0008574019 scopus 로고
    • Pa7200: A pa-rise processor with integrated high performance mp bus interface
    • Kurpanek, G., Chan, K., Zheng, J., DeLano, E., Bryg, W: Pa7200: A pa-rise processor with integrated high performance mp bus interface. In: COMPCON. (1994) 375-382
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.