Design of the HP PA 7200 CPU

Hewlett-Packard Journal

Volumn 47, Issue 1, 1996, Pages 25-33

  Chan, Kennethk ^a   Hay, Cyrusc ^a   Keller, Johnr ^a   Kurpanek, Gordonp ^a   Schumacher, Francisx ^a   Zheng, Jason ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER WORKSTATIONS; DATA HANDLING; INTEGRATED CIRCUIT MANUFACTURE; INTERFACES (COMPUTER); MULTIPROCESSING SYSTEMS; NETWORK PROTOCOLS; PERFORMANCE; PIPELINE PROCESSING SYSTEMS; VLSI CIRCUITS;

CENTRAL PROCESSING UNIT; DATA CACHE ORGANIZATION; FOUR WAY MULTIPROCESSOR SYSTEM; INTEGER SUPERSCALAR EXECUTION; PROCESSOR CHIP; TRANSLATION LOOKASIDE BUFFER;

MICROPROCESSOR CHIPS;

EID: 0030086672     PISSN: 00181153     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (14)

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11. E. Rashid, et al, "A CMOS RISC CPU with on-chip Parallel Cache," ISSCC Diueat of Technical Papers, February 1994.
12. T Asprey, et al, "Performance Features of the PA 7100 Microprocessor," IEEE Micro, June 1993, pp. 22-35.
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