Automatic tuning of two-level caches to embedded applications

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 208-213

  Gordon Ross, Ann ^a   Vahid, Frank ^a,b   Dutt, Nikil ^c  

^a University of California Riverside   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Ringgold Standard Institution Informatics   (United States)

Author keywords

Architecture tuning; Cache exploration; Cache hierarchy; Cache optimization; Configurable cache; Embedded systems; Low energy; Low power

Indexed keywords

CACHE EXPLORATION; CACHE HIERARCHY; CONFIGURABLE CACHE; ARCHITECTURE TUNING; CACHE HIERARCHIES; CACHE OPTIMIZATION; LOW ENERGY; LOW POWER;

COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SOFTWARE; ELECTRIC POWER UTILIZATION; EMBEDDED SYSTEMS; HEURISTIC METHODS; HIERARCHICAL SYSTEMS; MICROPROCESSOR CHIPS; OPTIMIZATION; TUNING; AUTOMATION; CACHE MEMORY; ENERGY UTILIZATION; EXHIBITIONS; HARDWARE;

BUFFER STORAGE; OPTIMIZATION;

EID: 3042558290     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268850     Document Type: Conference Paper

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