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Volumn 3553, Issue , 2005, Pages 455-464

A case for visualization-integrated system-level design space exploration

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; DATA REDUCTION; SYSTEMS ANALYSIS; VISUALIZATION;

EID: 26444454867     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/11512622_48     Document Type: Conference Paper
Times cited : (1)

References (43)
  • 3
    • 26444478317 scopus 로고    scopus 로고
    • System level design flow: What is needed and what is not
    • CECS, University of California at Irvine CECS-TR-02-33
    • Gajski, D.D.: System Level Design Flow: What is needed and What is not. Technical report, CECS, University of California at Irvine (2002) CECS-TR-02-33.
    • (2002) Technical Report
    • Gajski, D.D.1
  • 4
    • 0344951184 scopus 로고    scopus 로고
    • Metropolis: An integrated electronic system design environment
    • F. Balarin et al.: Metropolis: An integrated electronic system design environment. IEEE Computer 36 (2003)
    • (2003) IEEE Computer , vol.36
    • Balarin, F.1
  • 6
    • 84949452922 scopus 로고    scopus 로고
    • Rapid system-level performance evaluation and optimization for application mapping onto SoC architectures
    • Mohanty, S., Prasanna, V.K.: Rapid system-level performance evaluation and optimization for application mapping onto SoC architectures. In: Proc. of the IEEE International ASIC/SOC Conference. (2002)
    • (2002) Proc. of the IEEE International ASIC/SOC Conference
    • Mohanty, S.1    Prasanna, V.K.2
  • 8
    • 26444566457 scopus 로고    scopus 로고
    • The Artemis workbench for system-level performance evaluation of embedded systems
    • Pimentel, A.D.: The Artemis workbench for system-level performance evaluation of embedded systems. Int. Journal of Embedded Systems (2005)
    • (2005) Int. Journal of Embedded Systems
    • Pimentel, A.D.1
  • 17
    • 1142299899 scopus 로고    scopus 로고
    • Transaction level modeling: An overview
    • Cai, L., Gajski, D.: Transaction level modeling: An overview. In: Proc. of CODES-ISSS. (2003) 19-24
    • (2003) Proc. of CODES-ISSS , pp. 19-24
    • Cai, L.1    Gajski, D.2
  • 28
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new SoC paradigm
    • Benini, L., Micheli, G.D.: Networks on chips: A new SoC paradigm. IEEE Computer 35 (2002) 70-80
    • (2002) IEEE Computer , vol.35 , pp. 70-80
    • Benini, L.1    Micheli, G.D.2
  • 32
    • 0032278814 scopus 로고    scopus 로고
    • A hierarchical computer architecture design and simulation environment
    • P. S. Coe et al.: A hierarchical computer architecture design and simulation environment. ACM TOMACS 8 (1998) 431-446
    • (1998) ACM TOMACS , vol.8 , pp. 431-446
    • Coe, P.S.1
  • 40
    • 0003660988 scopus 로고    scopus 로고
    • MoML - A Modeling Markup Language in XML, version 0.4
    • Electronics Research Lab, University of California, Berkeley
    • Lee, E.A., Neuendorffer, S.: MoML - a Modeling Markup Language in XML, version 0.4. Technical Report UCB/ERL M00/8, Electronics Research Lab, University of California, Berkeley (2000)
    • (2000) Technical Report , vol.UCB-ERL M00-8
    • Lee, E.A.1    Neuendorffer, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.