Rapid system-level performance evaluation and optimization for application mapping onto SoC architectures

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn 2002-January, Issue , 2002, Pages 160-167

  Mohanty, Sumit ^a   Prasanna, Viktor K ^a  

^a University of Southern California ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; MAPPING; MICROPROCESSOR CHIPS; OPTIMIZATION; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP; VOLTAGE SCALING;

EFFICIENT DESIGN SPACE EXPLORATIONS; HETEROGENEOUS COMPONENT; HIERARCHICAL SIMULATION; OPTIMIZATION PROBLEMS; PERFORMANCE ESTIMATOR; PERFORMANCE OPTIMIZATIONS; SYSTEM-LEVEL PERFORMANCE EVALUATIONS; SYSTEM-ON-CHIP ARCHITECTURE;

INTEGRATED CIRCUIT DESIGN;

EID: 84949452922     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.2002.1158049     Document Type: Conference Paper

References (12)

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