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Volumn 52, Issue 7, 2005, Pages 1376-1383

Lateral high-speed bipolar transistors on SOI for RF SoC applications

Author keywords

BiCMOS integrated circuits; Lateral bipolar junction transistors (LBJTs); Microwave transistors; Radio frequency (RF) system on chip (RF SoC); Silicon bipolar transistors; Siliconon insulator (SOI)technology

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC RESISTANCE; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE STRUCTURES; SILICON ON INSULATOR TECHNOLOGY;

EID: 23944482251     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.850676     Document Type: Article
Times cited : (32)

References (22)
  • 1
    • 0038236470 scopus 로고    scopus 로고
    • "SiGe HBT and BiCMOS technologies for optical transmission and wireless communication systems"
    • Mar.
    • K. Washio, "SiGe HBT and BiCMOS technologies for optical transmission and wireless communication systems," IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 656-668, Mar. 2003.
    • (2003) IEEE Trans. Electron Devices , vol.50 , Issue.3 , pp. 656-668
    • Washio, K.1
  • 3
    • 33645434377 scopus 로고    scopus 로고
    • "Direction to improve SiGe BiCMOS technology featuring 200-GHz SiGe HBT and 80-nm GAT CMOS"
    • T. Hashimoto et al., "Direction to improve SiGe BiCMOS technology featuring 200-GHz SiGe HBT and 80-nm GAT CMOS," in IEDM Tech. Dig., 2003, pp. 5.5.1-5.5.4.
    • (2003) IEDM Tech. Dig.
    • Hashimoto, T.1
  • 4
    • 0011732087 scopus 로고    scopus 로고
    • "RF-SoC - Expectations and required conditions"
    • Jan.
    • A. Matsuzawa,"RF-SoC - Expectations and required conditions," IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 245-253, Jan. 2002.
    • (2002) IEEE Trans. Microw. Theory Tech. , vol.50 , Issue.1 , pp. 245-253
    • Matsuzawa, A.1
  • 5
    • 0034790451 scopus 로고    scopus 로고
    • "A 0.13-μm SOI CMOS technology for low-power digital and RF applications"
    • N. Zamdmer et al., "A 0.13-μm SOI CMOS technology for low-power digital and RF applications," in VLSI Symp. Tech. Dig., 2001, pp. 85-86.
    • (2001) VLSI Symp. Tech. Dig. , pp. 85-86
    • Zamdmer, N.1
  • 7
    • 6644223174 scopus 로고    scopus 로고
    • "Current status and future trends of SiGe BiCMOS technology"
    • Nov.
    • D. L. Harame et al., "Current status and future trends of SiGe BiCMOS technology," IEEE Trans. Electron Devices, vol. 48, no. 11, pp. 2575-2594, Nov. 2001.
    • (2001) IEEE Trans. Electron Devices , vol.48 , Issue.11 , pp. 2575-2594
    • Harame, D.L.1
  • 8
    • 0036256861 scopus 로고    scopus 로고
    • "A simple, high performance TFSOI complementary BiCMOS technology for low power wireless applications"
    • Jan.
    • M. Kumar, Y. Tan, and J. K. Sin, "A simple, high performance TFSOI complementary BiCMOS technology for low power wireless applications," IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 200-202, Jan. 2003.
    • (2003) IEEE Trans. Electron Devices , vol.49 , Issue.1 , pp. 200-202
    • Kumar, M.1    Tan, Y.2    Sin, J.K.3
  • 9
    • 0042941650 scopus 로고    scopus 로고
    • "Optimizing dynamic-threshold DTMOS device performance in an SOI embedded DRAM technology"
    • F. Burke, C. S. Kim, A. Rambhatla, Y. Zhao, J. Zahurak, and S. Parke, "Optimizing dynamic-threshold DTMOS device performance in an SOI embedded DRAM technology," in Proc. UGIMS., 2003, pp. 292-294.
    • (2003) Proc. UGIMS , pp. 292-294
    • Burke, F.1    Kim, C.S.2    Rambhatla, A.3    Zhao, Y.4    Zahurak, J.5    Parke, S.6
  • 10
    • 0036475861 scopus 로고    scopus 로고
    • max 6.7 ps ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications"
    • Feb.
    • max 6.7 ps ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications," IEEE Trans. Electron Devices, vol. 49, no. 2, pp. 271-278, Feb. 2002.
    • (2002) IEEE Trans. Electron Devices , vol.49 , Issue.2 , pp. 271-278
    • Washio, K.1
  • 11
    • 0036045977 scopus 로고    scopus 로고
    • "Fully depleted-collector polysilicon-emitter SiGe-base vertical bipolar transistor on SOI"
    • J. Cai, A. Ajmera, C. Ouyang, P. Oldiges, M. Steigerwalt, and K. Stein, "Fully depleted-collector polysilicon-emitter SiGe-base vertical bipolar transistor on SOI," in Proc. VLS1Symp., 2002, pp. 172-173.
    • (2002) Proc. VLSI Symp. , pp. 172-173
    • Cai, J.1    Ajmera, A.2    Ouyang, C.3    Oldiges, P.4    Steigerwalt, M.5    Stein, K.6
  • 12
    • 33645443314 scopus 로고    scopus 로고
    • "A simulation study on thin SOl bipolar transistors with fully or partially depleted collector"
    • Q. Quyang, J. Cai, T. Ning, P. Oldiges, and J. B. Johnson, "A simulation study on thin SOl bipolar transistors with fully or partially depleted collector," in Proc. BCTM, 2002, pp. 28-31.
    • (2002) Proc. BCTM , pp. 28-31
    • Quyang, Q.1    Cai, J.2    Ning, T.3    Oldiges, P.4    Johnson, J.B.5
  • 13
    • 0027878001 scopus 로고
    • "An ultra low power lateral bipolar polysilicon emitter technology on SOI"
    • R. Dekker, W. T. A. v. d. Einden, and H. G. R. Mass, "An ultra low power lateral bipolar polysilicon emitter technology on SOI," in IEDM Tech. Dig., 1993, pp. 75-78.
    • (1993) IEDM Tech. Dig. , pp. 75-78
    • Dekker, R.1    Einden, W.T.A.V.D.2    Mass, H.G.R.3
  • 16
    • 0042026500 scopus 로고    scopus 로고
    • "Fabrication of horizontal current bipolar transistor (HCBT)"
    • Jul.
    • T. Suligoj, M. Koricic, P. Bijanovic, and K. L. Wang, "Fabrication of horizontal current bipolar transistor (HCBT)," IEEE Trans. Electron Devices, vol. 50, no. 7, pp. 1645-1651, Jul. 2003.
    • (2003) IEEE Trans. Electron Devices , vol.50 , Issue.7 , pp. 1645-1651
    • Suligoj, T.1    Koricic, M.2    Bijanovic, P.3    Wang, K.L.4
  • 17
    • 0036494003 scopus 로고    scopus 로고
    • "Technological requirements for a lateral SiGe HBT technology including theoretical performance predictions relative to vertical SiGe HBTs"
    • Mar.
    • J. S. Hamel, Y. T. Tang, and K. Osman, "Technological requirements for a lateral SiGe HBT technology including theoretical performance predictions relative to vertical SiGe HBTs," IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 449-456, Mar. 2002.
    • (2002) IEEE Trans. Electron Devices , vol.49 , Issue.3 , pp. 449-456
    • Hamel, J.S.1    Tang, Y.T.2    Osman, K.3
  • 18
    • 29044440093 scopus 로고    scopus 로고
    • "FinFET-A self-aligned double-gate MOSFET scalable to 20 nm"
    • Dec.
    • D. Hisamoto et al., "FinFET-A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
    • (2000) IEEE Trans. Electron Devices , vol.47 , Issue.12 , pp. 2320-2325
    • Hisamoto, D.1
  • 19
    • 0024766197 scopus 로고
    • "Shadowing effects de to tilted arsenic source/drain implants"
    • Nov.
    • G. Krieger, G. Spadini, P. P. Guevas, and J. Schuur, "Shadowing effects de to tilted arsenic source/drain implants," IEEE Trans. Electron Devices, vol. 26, no. 11, pp. 2458-2461, Nov. 1989.
    • (1989) IEEE Trans. Electron Devices , vol.26 , Issue.11 , pp. 2458-2461
    • Krieger, G.1    Spadini, G.2    Guevas, P.P.3    Schuur, J.4
  • 20
    • 0028397615 scopus 로고
    • "Drain structure optimization for highly reliable deep submicrometer n-channel MOSFET"
    • Mar.
    • F. Matsuoka, K. Kasai, H. Oyamatsu, M. Kinugawa, and K. Maeguchi, "Drain structure optimization for highly reliable deep submicrometer n-channel MOSFET," IEEE Trans. Electron Devices, vol. 41, no. 3, pp. 420-426, Mar. 1994.
    • (1994) IEEE Trans. Electron Devices , vol.41 , Issue.3 , pp. 420-426
    • Matsuoka, F.1    Kasai, K.2    Oyamatsu, H.3    Kinugawa, M.4    Maeguchi, K.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.