Optimizing dynamic-threshold DTMOS device performance in an SOI embedded DRAM technology

Biennial University/Government/Industry Microelectronics Symposium - Proceedings

Volumn , Issue , 2003, Pages 292-294

  Burke, F ^a   Kim, C S ^a   Rambhatla, A ^a   Zhao, Y ^a   Zahurak, J ^b   Parke, S ^a  

^a Boise State University   (United States)

^b MICRON TECHNOLOGY INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC CURRENTS; MOSFET DEVICES; NETWORKS (CIRCUITS); SILICON ON INSULATOR TECHNOLOGY;

GROUNDED BODIES (GB);

MOS DEVICES;

EID: 0042941650     PISSN: 07496877     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. D. Goldman, et al, SOI Conf, pp. 236-238, Oct. 2001.
2. S. Parke, et al, EDL, Vol. 14, No. 5, pp. 236-238, May 1993.
3. F. Assaderaghi, et al, IEDM, pp. 809-812, Dec. 1994.
4. F. Assaderaghi, et al, TED, Vol.44, pp. 414-422, Mar. 1997.
5. T. Tanaka, et al, IEDM, pp. 423-426, Dec. 1997
6. V. Ferlet-Cavrois, et al, SOI Conf., pp. 24-25, Oct. 1999.
7. Y. Momiyama, et al, IEDM, pp., Dec. 2000.
8. A. Yagishita, et al, IEDM, pp., Dec. 2000.