Short-channel single-gate SOI MOSFET model

IEEE Transactions on Electron Devices

Volumn 50, Issue 5, 2003, Pages 1297-1305

  Suzuki, Kunihiro ^a   Pidin, Sergey ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

MOSFET; Short channel effects; Silicon on insulator (SOI)

Indexed keywords

COMPUTER SIMULATION; GATES (TRANSISTOR); MATHEMATICAL MODELS; NUMERICAL ANALYSIS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

BURIED OXIDE LAYERS; SHORT CHANNEL EFFECTS;

MOSFET DEVICES;

EID: 0041672298     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.813450     Document Type: Article

References (14)

1. K. K. Young, "Short-channel effect in fully depleted SOI MOSFETs," IEEE Trans. Electron Devices, vol. 36, pp. 399-401, 1989.
2. ____, "Analysis of conduction in fully depleted SOI MOSFETs," IEEE Trans. Electron Devices, vol. 36, pp. 504-506, 1989.
3. R. H. Yan, A. Ourmazd, and K. F. Lee, "Scaling the Si MOSFET: From bulk to SOI to bulk," IEEE Trans. Electron Devices, vol. 39, pp. 1704-1710, 1992.
4. H.-O. Yoachim, Y. Yamaguchi, K. Ishikawa, Y. Inoue, and T. Nishimura, "Simulation and 2D analytical modeling of sub threshold slope in ultra thin-film SOI MOSFETs down to 0.1 μm gate length," IEEE Trans. Electron Devices, vol. 40, pp. 1812-1817, 1993.
5. S. R. Banna, P. C. H. Chan, P. K. Ko, C. T. Nguyen, and M. Chan, "Threshold voltage model for deep-submicrometer fully depleted SOI MOSFETs," IEEE Trans. Electron Devices, vol. 42, pp. 1949-1955, 1995.
6. S. Pidin and M. Koyanagi, "Two-dimensional analytical subthreshold model and optimal scaling of fully-depleted SOI MOSFET down to 0.1 μm channel length," in Solid State Devices Mat. Tech. Dig., 1996, pp. 309-310.
7. K. Suzuki, Y. Tosaka, T. Tanaka, H. Horie, and Y. Arimoto, "Scaling theory for double-gate SOI MOSFETs," IEEE Trans. Electron Devices, vol. 40, pp. 2326-2329, 1993.
8. + double-gate SOI MOSFETs," IEEE Trans. Electron Devices, vol. 42, pp. 1940-1948, 1995.
9. T. K. Chiang, Y. H. Wang, and M. P. Houng, "Modeling of threshold voltage and subthreshold swing of short-channel SOI MOSFETs," Solid-State Electron, vol. 43, pp. 123-129, 1999.
10. D. J. Frank, Y. Taur, and H.-S. P. Wong, "Generalized scale length for 2D effects in MOSFETs," IEEE Trans. Electron Devices, vol. ED-19, pp. 385-387.
11. S.-L. Jang, B.-R. Huang, and J.-J. Ju, "A unified analytical fully depleted and partially depleted SOI MOSFET model," IEEE Trans. Electron Devices, vol. 46, pp. 1872-1876, 1998.
12. Medici User's Manual: Avanti! Corp.
13. K. Suzuki, "Short channel epi-MOSFET model," IEEE Trans. Electron Devices, vol. 47, pp. 2372-2378, Dec. 2000.
14. T. Ghani, S. Ahmed, P. Aminzadef, J. Ielefeld, P. Charvat, C. Chu, M. Harper, P. Jacob, C. Jan, J. Kavalalieros, C. Kenyon, R. Nagisetty, P. Packan, J. Sebastian, M. Taylor, J. Tsai, S. Tyagi, S. Yang, and M. Bohr, "100 nm gate length high performance/low power CMOS transistor structure," in IEDM Tech. Dig., 1999, pp. 415-4158.