Design of sub-50nm Ultrathin-Body (UTB) SOI MOSFETs with raised S/D

2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

Volumn , Issue , 2003, Pages 251-254

  Xusheng, Wu ^a   Shengdong, Zhang ^b   Chan, Mansun ^b   Chan, Philip ^b  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; DIELECTRIC MATERIALS; ELECTRIC RESISTANCE; ELECTRON DEVICES; MOSFET DEVICES;

2-D DEVICE SIMULATIONS; DEVICE PERFORMANCE; GATE-TO-DRAIN CAPACITANCE; LOW K DIELECTRICS; PARASITIC CAPACITANCE; SOI-MOSFETS; SOURCE/DRAIN SERIES RESISTANCES; ULTRA-THIN BODY (UTB) SOI;

SOLID STATE DEVICES;

EID: 84946411179     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDSSC.2003.1283525     Document Type: Conference Paper

References (5)

1. International Technology Roadmap for Semiconductor, 2001.
2. Meikei Ieong, et al, Quality Electron Design, proceedings, p492-495 2002.
3. Mansun Chan, et al, IEEE EDL, vol.15, p22-24, 1994.
4. Yang-Kyu Choi, et al, VLSI Tec. p.19-20, 2001.
5. C.S. Yin, et al, EDM, proceedings. IEEE HK, p.89-92, 2001.