Transistor operation of 30-nm gate-length EJ-MOSFETs

IEEE Electron Device Letters

Volumn 19, Issue 3, 1998, Pages 74-76

  Kawaura, Hisao ^a   Sakamoto, Toshitsugu ^a   Baba, Toshio ^a   Ochiai, Yukinori ^a   Fujita, Jun'ichi ^a   Matsui, Shinji ^a   Sone, Jun'ichi ^a  

^a NEC CORPORATION   (Japan)

Author keywords

30 nm gate length; EJ MOSFET; Ultrashallow source drain

Indexed keywords

ELECTRIC CURRENTS; ELECTRON BEAMS; FABRICATION; PHOTOLITHOGRAPHY; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR JUNCTIONS;

CALIXARENE; CUTOFF CURRENT; ELECTRON BEAM DIRECT WRITING; GATE LENGTH; SHORT CHANNEL EFFECT; ULTRASHALLOW SOURCE DRAIN REGION;

MOSFET DEVICES;

EID: 0032026488     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.661169     Document Type: Article

References (4)

1. M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Oguro, and H. Iwai, "Sub-50 nm gate length N-MOSFET's with 10-nm phosphorus source and drain junctions," in IEDM Tech. Dig., 1993, pp. 119-122.
2. Y. Ochiai, S. Manako, S. Samukawa, K. Takeuchi, and T. Yamamoto, "Accurate nano-EB lithography for 40-nm gate MOSFET's," Microelectron. Eng., vol. 30, pp. 415-418, 1996.
3. H. Noda, F. Murai, and S. Kimura, "Threshold voltage controlled 0.1-μm MOSFET utilizing inversion layer as extremely shallow source/drain," in IEDM Tech. Dig., 1993, pp. 123-126.
4. H. Kawaura, T. Sakamoto, T. Baba, Y. Ochiai, J. Fujita, S. Matsui, and J. Sone, "Proposal of pseudo source and drain MOSFET's and evaluation for 10-nm gate MOSFET's," in Ext. Abstr. Int. Conf. Solid State Devices and Mater., 1996, pp. 22-24.