The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 8, 2005, Pages 1751-1759

  Ker, Ming Dou ^a   Lin, Kun Hsien ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Electrostatic discharge (ESD); Latchup; Power rail ESD clamp circuit; Transient latchup (TLU); Transmission line pulsing (TLP)

Indexed keywords

CAPACITANCE; DIFFUSION; ELECTRIC DISCHARGES; ELECTRIC LINES; ELECTRIC POTENTIAL; ELECTROSTATICS; GATES (TRANSISTOR); LIQUID CRYSTAL DISPLAYS;

ELECTROSTATIC DISCHARGE (ESD); LATCHUP; POWER-RAIL ESD CLAMPED CIRCUIT; TRANSIENT LATCHUP (TLU); TRANSMISSION LINE PULSING (TLP);

CMOS INTEGRATED CIRCUITS;

EID: 23744434359     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.852046     Document Type: Article

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