-
1
-
-
0032273088
-
Electrostatic discharge protection circuits in CMOS IC's using the lateral SCR devices: An overview
-
M.-D. Ker, "Electrostatic discharge protection circuits in CMOS IC's using the lateral SCR devices: An overview," in Proc. IEEE Int. Conf. Electronics Circuits and Systems, 1998, pp. 325-328.
-
(1998)
Proc. IEEE Int. Conf. Electronics Circuits and Systems
, pp. 325-328
-
-
Ker, M.-D.1
-
2
-
-
0024174395
-
ESD protection for submicron CMOS circuits: Issues and solutions
-
R. N. Rountree, "ESD protection for submicron CMOS circuits: Issues and solutions," in IEDM Tech. Dig., 1988, pp. 580-583.
-
(1988)
IEDM Tech. Dig.
, pp. 580-583
-
-
Rountree, R.N.1
-
3
-
-
0026391378
-
A synthesis of ESD input protection scheme
-
C. Duvvury and R. Rountree, "A synthesis of ESD input protection scheme," in Proc. EOS/ESD Symp., 1991, pp. 88-97.
-
(1991)
Proc. EOS/ESD Symp.
, pp. 88-97
-
-
Duvvury, C.1
Rountree, R.2
-
4
-
-
0025953251
-
A low-voltage triggering SCR for on-chip ESD protection at output and input pads
-
A. Chatterjee and T. Polgreen, "A low-voltage triggering SCR for on-chip ESD protection at output and input pads," IEEE Electron Device Lett., vol. 12, pp. 21-22, 1991.
-
(1991)
IEEE Electron Device Lett.
, vol.12
, pp. 21-22
-
-
Chatterjee, A.1
Polgreen, T.2
-
5
-
-
0030128946
-
Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI
-
M.-D. Ker, C.-Y. Wu, H.-H. Chang, and T.-S. Wu, "Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI," IEEE Trans. Electron Devices, vol. 43, pp. 588-598, 1996.
-
(1996)
IEEE Trans. Electron Devices
, vol.43
, pp. 588-598
-
-
Ker, M.-D.1
Wu, C.-Y.2
Chang, H.-H.3
Wu, T.-S.4
-
6
-
-
0030836964
-
A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's
-
M.-D. Ker, H.-H. Chang, and C.-Y. Wu, "A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's," IEEE J. Solid-State Circuits, vol. 32, pp. 38-51, 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, pp. 38-51
-
-
Ker, M.-D.1
Chang, H.-H.2
Wu, C.-Y.3
-
7
-
-
0031641250
-
Novel input ESD protection circuit with substrate-triggering technique in a 0.25-μm shallow-trench-isolation CMOS technology
-
M.-D. Ker, T.-Y. Chen, C.-Y. Wu, H. Tang, K.-C. Su, and S.-W. Sun, "Novel input ESD protection circuit with substrate-triggering technique in a 0.25-μm shallow-trench-isolation CMOS technology," in Proc. IEEE Int. Symp. Circuits and System, vol. 2, 1998, pp. 212-215.
-
(1998)
Proc. IEEE Int. Symp. Circuits and System
, vol.2
, pp. 212-215
-
-
Ker, M.-D.1
Chen, T.-Y.2
Wu, C.-Y.3
Tang, H.4
Su, K.-C.5
Sun, S.-W.6
-
8
-
-
84888038303
-
ESD protection design in a 0.18-μm salicide CMOS technology by using substrate-triggered technique
-
M.-D. Ker, T.-Y. Chen, and C.-Y. Wu, "ESD protection design in a 0.18-μm salicide CMOS technology by using substrate-triggered technique," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 4, 2001, pp. 754-757.
-
(2001)
Proc. IEEE Int. Symp. Circuits and Systems
, vol.4
, pp. 754-757
-
-
Ker, M.-D.1
Chen, T.-Y.2
Wu, C.-Y.3
-
9
-
-
84948982831
-
GGSCR: GGNMOS triggered silicon controlled rectifiers for ESD protection in deep submicron CMOS processes
-
C. RUSS, M. Mergens, J. Armer, P. Jozwiak, G. Kolluri, L. Avery, and K. Verhaege, "GGSCR: GGNMOS triggered silicon controlled rectifiers for ESD protection in deep submicron CMOS processes," in Proc. EOS/ESD Symp., 2001, pp. 22-31.
-
(2001)
Proc. EOS/ESD Symp.
, pp. 22-31
-
-
Russ, C.1
Mergens, M.2
Armer, J.3
Jozwiak, P.4
Kolluri, G.5
Avery, L.6
Verhaege, K.7
-
10
-
-
0036287788
-
On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process
-
M.-D. Ker and K.-C. Hsu, "On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process," in Proc. IEEE Int. Symp. Circuits and Systems, 2002, pp. 529-532.
-
(2002)
Proc. IEEE Int. Symp. Circuits and Systems
, pp. 529-532
-
-
Ker, M.-D.1
Hsu, K.-C.2
-
11
-
-
0024123504
-
Hot-electron reliability and ESD latent damage
-
S. Aur, A. Chatterjee, and T. Polgreen, "Hot-electron reliability and ESD latent damage," IEEE Trans. Electron Devices, vol. 35, pp. 2189-2193, 1988.
-
(1988)
IEEE Trans. Electron Devices
, vol.35
, pp. 2189-2193
-
-
Aur, S.1
Chatterjee, A.2
Polgreen, T.3
-
12
-
-
0025503641
-
Impact of snapback-induced hole injection on gate oxide reliability of N-MOSFET's
-
K. R. Mistry, D. Krakauer, and B. S. Doyle, "Impact of snapback-induced hole injection on gate oxide reliability of N-MOSFET's," IEEE Electron Device Lett., vol. 11, pp. 460-462, 1990.
-
(1990)
IEEE Electron Device Lett.
, vol.11
, pp. 460-462
-
-
Mistry, K.R.1
Krakauer, D.2
Doyle, B.S.3
-
13
-
-
0029544242
-
Transient-induced latchup testing of CMOS integrated circuits
-
G. Weiss and D. Young, "Transient-induced latchup testing of CMOS integrated circuits," in Proc. EOS/ESD Symp., 1995, pp. 194-198.
-
(1995)
Proc. EOS/ESD Symp.
, pp. 194-198
-
-
Weiss, G.1
Young, D.2
-
15
-
-
0032740282
-
SS ESD clamp circuits for submicron CMOS VLSI
-
SS ESD clamp circuits for submicron CMOS VLSI," IEEE Trans. Electron Devices, vol. 46, pp. 173-183, 1999.
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, pp. 173-183
-
-
Ker, M.-D.1
-
16
-
-
0022212124
-
Transmission line pulsing techniques for circuit modeling of ESD phenomena
-
T. J. Maloney and N. Khurana, "Transmission line pulsing techniques for circuit modeling of ESD phenomena," in Proc. EOS/ESD Symp., 1985, pp. 49-54.
-
(1985)
Proc. EOS/ESD Symp.
, pp. 49-54
-
-
Maloney, T.J.1
Khurana, N.2
-
17
-
-
0003126888
-
TLP calibration, correlation, standards, and new techniques
-
J. Earth, J. Richner, K. Verhaege, and L. G. Henry, "TLP calibration, correlation, standards, and new techniques," in Proc. EOS/ESD Symp., 2000, pp. 85-96.
-
(2000)
Proc. EOS/ESD Symp.
, pp. 85-96
-
-
Earth, J.1
Richner, J.2
Verhaege, K.3
Henry, L.G.4
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