-
1
-
-
33747412808
-
-
1C's, Technologies, and Applications, 1st ed. Berlin, Germany: Springer-Verlag, 1995, pp. 56-60.
-
B. Murari, F. Bertotti, and G. A. Vignola, Smart Power 1C's, Technologies, and Applications, 1st ed. Berlin, Germany: Springer-Verlag, 1995, pp. 56-60.
-
F. Bertotti, and G. A. Vignola, Smart Power
-
-
Murari, B.1
-
3
-
-
84886448166
-
-
1EDM Tech. Dig., 1997, pp. 375-378.
-
C. Duvvury, F. Carvajal, C. Jones, and D. Briggs, "Lateral DMOS design for ESD robustness," in 1EDM Tech. Dig., 1997, pp. 375-378.
-
F. Carvajal, C. Jones, and D. Briggs, "Lateral DMOS Design for ESD Robustness," in
-
-
Duvvury, C.1
-
4
-
-
33747400052
-
-
40V-LDMOS power devices under ESD stress conditions," in Proc. 21st EOS/ESD Symp., Orlando, FL, 1999, pp. 1-10.
-
M. Mergens et al., "Analysis and compact modeling of 40V-LDMOS power devices under ESD stress conditions," in Proc. 21st EOS/ESD Symp., Orlando, FL, 1999, pp. 1-10.
-
"Analysis and Compact Modeling of
-
-
Mergens, M.1
-
5
-
-
33747436059
-
-
1998.
-
ISE Integrated Syst. Eng. AG, Zurich, "Modeling of Semiconductor Technology, Devices and Systems"-ISE TCAD Manuals, Zurich, Switzerland, 1998.
-
Zurich, "Modeling of Semiconductor Technology, Devices and Systems"-ISE TCAD Manuals, Zurich, Switzerland
-
-
-
6
-
-
0032678897
-
-
1999, pp. 167-178.
-
M. Mergens et al., "Modular approach of a high current MOS compact model for circuit-level ESD simulation including transient gate coupling behavior," in Proc. Int. Reliability Physics Symp., San Diego, CA, 1999, pp. 167-178.
-
"Modular Approach of A High Current MOS Compact Model for Circuit-level ESD Simulation Including Transient Gate Coupling Behavior," in Proc. Int. Reliability Physics Symp., San Diego, CA
-
-
Mergens, M.1
-
7
-
-
0000155267
-
-
105, pp. 1246-1249, 1957.
-
S. L. Miller, "lonization rates for holes and electrons in silicon," Phys. Rev., vol. 105, pp. 1246-1249, 1957.
-
"Lonization Rates for Holes and Electrons in Silicon," Phys. Rev., Vol.
-
-
Miller, S.L.1
-
8
-
-
0030421382
-
-
0.25 ftm CMOS process," in IEDM Tech. Dig., 1996, pp. 893-896.
-
A. Amerasekera, V. McNeil, and M. Rodder, "Correlating drain junction scaling, salicide thickness, and lateral NPN behavior, with the EOS/ESD performance of a 0.25 ftm CMOS process," in IEDM Tech. Dig., 1996, pp. 893-896.
-
V. McNeil, and M. Rodder, "Correlating Drain Junction Scaling, Salicide Thickness, and Lateral NPN Behavior, with the EOS/ESD Performance of A
-
-
Amerasekera, A.1
-
10
-
-
84920730943
-
-
25th ESSDERC Conf., The Netherlands, 1995, pp. 307-310.
-
J. R. M. Luchies et al, "Fast transient ESD simulation of the nMOS protection transistor," in Proc. 25th ESSDERC Conf., The Netherlands, 1995, pp. 307-310.
-
"Fast Transient ESD Simulation of the NMOS Protection Transistor," in Proc.
-
-
Luchies, J.R.M.1
-
11
-
-
0031277335
-
-
44, no. 11, pp. 1972-1980, 1997.
-
K. Verhaege et al., "Grounded-gate nMOS transistor behavior under COM ESD stress conditions," IEEE Trans. Electron Devices, vol. 44, no. 11, pp. 1972-1980, 1997.
-
"Grounded-gate NMOS Transistor Behavior under COM ESD Stress Conditions," IEEE Trans. Electron Devices, Vol.
-
-
Verhaege, K.1
-
12
-
-
0020205140
-
-
11, pp. 1735-1740, 1982.
-
F.-C. Hsu et al, "An analytical breakdown model for short-channel MOSFET's," IEEE Trans. Electron Devices, vol. ED-29, no. 11, pp. 1735-1740, 1982.
-
"An Analytical Breakdown Model for Short-channel MOSFET's," IEEE Trans. Electron Devices, Vol. ED-29, No.
-
-
Hsu, F.-C.1
-
13
-
-
0020091286
-
-
254-266, Feb. 1982.
-
B. Eitan and D. Frohman-Bentchkowsky, "Surface conduction in shortchannel MOS devices as a limitation to VLSI scaling," IEEE Trans. Electron Devices, vol. ED-29, pp. 254-266, Feb. 1982.
-
"Surface Conduction in Shortchannel MOS Devices As A Limitation to VLSI Scaling," IEEE Trans. Electron Devices, Vol. ED-29, Pp.
-
-
Eitan, B.1
Frohman-Bentchkowsky, D.2
-
14
-
-
0026254123
-
-
11, pp. 2527-2529, 1991.
-
N. D. Jankovic, "Pre-turn-on source bipolar injection in graded NMOST's," IEEE Trans. Electron Devices, vol. ED-38, no. 11, pp. 2527-2529, 1991.
-
"Pre-turn-on Source Bipolar Injection in Graded NMOST's," IEEE Trans. Electron Devices, Vol. ED-38, No.
-
-
Jankovic, N.D.1
-
15
-
-
0020113843
-
-
77-85, 1982.
-
A. Schütz, S. Selberherr, and H. W. Pötzl, "Analysis of breakdown phenomena in MOSFET's," IEEE Trans. Computer-Aided Design, vol. CAD-1, pp. 77-85, 1982.
-
S. Selberherr, and H. W. Pötzl, "Analysis of Breakdown Phenomena in MOSFET's," IEEE Trans. Computer-Aided Design, Vol. CAD-1, Pp.
-
-
Schütz, A.1
-
16
-
-
0023346895
-
-
1066-1073, May 1987.
-
S. E. Laux and F. H. Gaensslen, "A study of channel avalanche breakdown in scaled n-MOSFET's," IEEE Trans. Electron Devices, vol. ED-34, pp. 1066-1073, May 1987.
-
"A Study of Channel Avalanche Breakdown in Scaled N-MOSFET's," IEEE Trans. Electron Devices, Vol. ED-34, Pp.
-
-
Laux, S.E.1
Gaensslen, F.H.2
-
18
-
-
33747387856
-
-
21st EOS/ESD Symp., Orlando, FL, 1999, pp. 241-249.
-
C. Fürböck et al., "Interferometric temperature mapping during ESD stress and failure analysis of smart power technology ESD protection devices," in Proc. 21st EOS/ESD Symp., Orlando, FL, 1999, pp. 241-249.
-
"Interferometric Temperature Mapping during ESD Stress and Failure Analysis of Smart Power Technology ESD Protection Devices," in Proc.
-
-
Fürböck, C.1
-
19
-
-
0026820351
-
-
39, p. 379, Feb. 1992.
-
T. Polgreen and A. Chatterjee, "Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow," IEEE Trans. Electron Devices, vol. 39, p. 379, Feb. 1992.
-
"Improving the ESD Failure Threshold of Silicided N-MOS Output Transistors by Ensuring Uniform Current Flow," IEEE Trans. Electron Devices, Vol.
-
-
Polgreen, T.1
Chatterjee, A.2
-
20
-
-
0026838967
-
-
1992, pp. 141-150.
-
C. Duvvury and C. H. Diaz, "Dynamic gate coupling of NMOS for efficient output ESD protection," in Proc. Int. Reliability Physics Symp., San Diego, CA, 1992, pp. 141-150.
-
"Dynamic Gate Coupling of NMOS for Efficient Output ESD Protection," in Proc. Int. Reliability Physics Symp., San Diego, CA
-
-
Duvvury, C.1
Diaz, C.H.2
-
21
-
-
0031352418
-
-
19th EOS/ESD Symp., Santa Clara, CA, 1997, pp. 230-238.
-
J. Z. Chen, A. Amerasekera, and C. Duvvury, "Design methodology for optimizing gate driven ESD protection circuits in submicron CMOS processes," in Proc. 19th EOS/ESD Symp., Santa Clara, CA, 1997, pp. 230-238.
-
A. Amerasekera, and C. Duvvury, "Design Methodology for Optimizing Gate Driven ESD Protection Circuits in Submicron CMOS Processes," in Proc.
-
-
Chen, J.Z.1
-
22
-
-
0032320896
-
-
20th EOS/ESD Symp., Reno, NV, 1998, pp. 177-186.
-
C. RUSS et al., "Non-uniform triggering of gg-nMOSt investigated by combined emission microscopy and transmission line pulsing," in Proc. 20th EOS/ESD Symp., Reno, NV, 1998, pp. 177-186.
-
"Non-uniform Triggering of Gg-nMOSt Investigated by Combined Emission Microscopy and Transmission Line Pulsing," in Proc.
-
-
Russ, C.1
-
23
-
-
0022212124
-
-
8th EOS/ESD Symp., Minneapolis, MN, 1985, pp. 49-54.
-
T. J. Maloney and N. Khurana, "Transmission line pulsing techniques for circuit modeling of ESD phenomena," in Proc. 8th EOS/ESD Symp., Minneapolis, MN, 1985, pp. 49-54.
-
"Transmission Line Pulsing Techniques for Circuit Modeling of ESD Phenomena," in Proc.
-
-
Maloney, T.J.1
Khurana, N.2
|