Novel ESD protection structure with embedded SCR LDMOS for smart power technology

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2002, Pages 156-161

  Lee, Jian Hsing ^a   Shih, J R ^a   Tang, C S ^a   Liu, K C ^a   Wu, Y H ^a   Shiue, R Y ^a   Ong, T C ^a   Peng, Y K ^a   Yue, J T ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Current distribution; Current measurement; Electrostatic discharge; Performance evaluation; Power transistors; Protection; Pulse measurements; Stress; Thyristors; Voltage

Indexed keywords

ELECTRIC CURRENT MEASUREMENT; ELECTRIC POTENTIAL; ELECTROSTATIC DISCHARGE; MOS DEVICES; POWER ELECTRONICS; STRESSES; THYRISTORS; TRANSISTORS; VOLTAGE CONTROL;

CURRENT DISTRIBUTION; PERFORMANCE EVALUATION; POWER TRANSISTORS; PROTECTION; PULSE MEASUREMENTS;

ELECTROSTATIC DEVICES;

EID: 84925292690     PISSN: 15417026     EISSN: None     Source Type: Journal    
DOI: 10.1109/RELPHY.2002.996629     Document Type: Article

References (5)

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2. C. Duvvury, F. Carvajal, C. Jones, and D. Briggs, "Lateral DMOS Design for ESD Robustness," in 1997 IEDM Tech.Dig., p. 375
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