Double snapback characteristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design

IEEE Electron Device Letters

Volumn 25, Issue 9, 2004, Pages 640-642

  Ker, Ming Dou ^a   Lin, Kun Hsien ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC BREAKDOWN; ELECTRIC CURRENT DISTRIBUTION; ELECTRIC POTENTIAL; ELECTROSTATICS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR JUNCTIONS; TRANSMISSION LINE THEORY;

DOUBLE DIFFUSED DRAIN; ELECTROSTATIC DISCHARGE PROTECTION; HIGH VOLTAGE MOSFET; LATERAL DIFFUSED MOS; TRANSMISSION LINE PULSING;

MOSFET DEVICES;

EID: 4444263243     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.833372     Document Type: Article

References (14)

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