Dynamically trading frequency for complexity in a GALS microprocessor

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2004, Pages 157-168

  Dropsho, Steven ^a,b   Semeraro, Greg ^a,c   Albonesi, David H ^a,d   Magklis, Grigorios ^a,e   Scott, Michael L ^a,f  

^a UNIVERSITY OF ROCHESTER   (United States)

^b EPFL IC LABOS   (Switzerland)

^c Kate Gleason College of Engineering   (United States)

^d Cornell University ^*  (United States)

^e INTEL RESEARCH   (United States)

^f University of Rochester   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK FREQUENCY; GLOBALLY ASYNCHRONOUS, LOCALLY SYNCHRONOUS (GALS); INSTRUCTION-LEVEL PARALLELISM (ILP); TRANSACTION PROCESSING;

COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; ELECTRIC POTENTIAL; MATHEMATICAL MODELS; MULTIMEDIA SYSTEMS; OPTIMIZATION; SYNCHRONIZATION;

MICROPROCESSOR CHIPS;

EID: 21644462451     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2004.18     Document Type: Conference Paper

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