Substrate interconnect technologies for 3-D MEMS packaging

Microelectronic Engineering

Volumn 81, Issue 1, 2005, Pages 106-116

  Morgan, Brian ^a   Hua, Xuefeng ^b,c   Iguchi, Tomohiro ^d   Tomioka, Taizo ^d   Oehrlein, Gottlieb S ^a,c   Ghodssi, Reza ^a  

^a UNIVERSITY OF MARYLAND   (United States)

^b Bldg 142   (United States)

^c The Institute for Research in Electronics and Applied Physics   (United States)

^d TOSHIBA CORPORATION   (Japan)

Author keywords

3 D substrate; DRIE; Gray scale lithography; Interconnects

Indexed keywords

ELECTROPLATING; ETCHING; EVAPORATION; INTEGRATED CIRCUITS; MOSFET DEVICES; SILICON; SUBSTRATES;

3-D SUBSTRATE; COPPER ELECTROPLATING; DEEP REACTION ION ETCHING (DRIE); GRAY-SCALE LITHOGRAPHY;

MICROELECTROMECHANICAL DEVICES;

EID: 21644445866     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2005.04.004     Document Type: Article

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