A plated through-hole interconnect technology in silicon

Journal of the Electrochemical Society

Volumn 144, Issue 7, 1997, Pages 2490-2495

  Jaafar, Maha A S ^a,b,c   Denton, Denice D ^a,d  

^a University of Wisconsin Madison   (United States)

^b ELECTROCHEMICAL SOCIETY   (United States)

^c Semiconductor Design International   (United States)

^d University of Washington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC RESISTANCE; ELECTRONICS PACKAGING; ELECTROPLATING; ETCHING; MULTILAYERS; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON SENSORS; SUBSTRATES;

INTERCONNECT TECHNOLOGY; PLATED THROUGH HOLE (PTH) PROCESS;

SEMICONDUCTING SILICON;

EID: 0031191554     PISSN: 00134651     EISSN: None     Source Type: Journal    
DOI: 10.1149/1.1837842     Document Type: Article

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