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Volumn , Issue , 2004, Pages 239-242

Integration of high-performance SiGe:C HBTs with thin-film SOI CMOS

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; ELECTRIC POTENTIAL; HETEROJUNCTION BIPOLAR TRANSISTORS; ION IMPLANTATION; SILICON WAFERS; THICKNESS MEASUREMENT; THIN FILMS; CMOS INTEGRATED CIRCUITS; SI-GE ALLOYS;

EID: 21644432295     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (14)

References (8)
  • 1
    • 4544286733 scopus 로고    scopus 로고
    • A 243-GHz Ft and 208-GHz Fmax, 90-nm SOI CMOS SoC technology with low-power millimeter wave digital and RF circuit capability
    • N. Zamdmer et al., "A 243-GHz Ft and 208-GHz Fmax, 90-nm SOI CMOS SoC technology with low-power millimeter wave digital and RF circuit capability", VLSI Technology Symposium 2004, pp. 98-99.
    • VLSI Technology Symposium 2004 , pp. 98-99
    • Zamdmer, N.1
  • 2
    • 4544385361 scopus 로고    scopus 로고
    • A comparison of state-of-the-art NMOS and SiGe HBT devices for analog/mixed-signal/RF circuit applications
    • K. Kuhn et al., "A comparison of state-of-the-art NMOS and SiGe HBT devices for analog/mixed-signal/RF circuit applications", VLSI Technology Symposium 2004, pp.224-225.
    • VLSI Technology Symposium 2004 , pp. 224-225
    • Kuhn, K.1
  • 3
    • 0036475861 scopus 로고    scopus 로고
    • A 0.2μm 180-GHz-fmax 6.7-ps-ECL SOI/HSR self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications
    • K. Washio et al., "A 0.2μm 180-GHz-fmax 6.7-ps-ECL SOI/HSR self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications" IEEE TED vol. 49, p. 271, 2002.
    • (2002) IEEE TED , vol.49 , pp. 271
    • Washio, K.1
  • 4
    • 1042289139 scopus 로고    scopus 로고
    • Vertical SiGe-base bipolar transistor on CMOS-compatible SOI-substrate
    • J. Cai et al., "Vertical SiGe-base bipolar transistor on CMOS-compatible SOI-substrate", BCTM 2003.
    • BCTM 2003
    • Cai, J.1
  • 5
    • 0036165797 scopus 로고    scopus 로고
    • The spacer/replacer concept: A viable route for sub-100 nm ultrathin-film fully-depleted SOI CMOS
    • H. v. Meer and K. De Meyer, "The spacer/replacer concept: A viable route for sub-100 nm ultrathin-film fully-depleted SOI CMOS", IEEE EDL vol. 23, pp. 46-48, 2002.
    • (2002) IEEE EDL , vol.23 , pp. 46-48
    • Meer, H.V.1    De Meyer, K.2
  • 6
    • 0842331404 scopus 로고    scopus 로고
    • SiGe:C BiCMOS technology with 3.6 ps gate delay
    • H. Rücker et al., "SiGe:C BiCMOS technology with 3.6 ps gate delay", IEDM 2003, pp. 121-124.
    • IEDM 2003 , pp. 121-124
    • Rücker, H.1
  • 7
    • 0036440040 scopus 로고    scopus 로고
    • BiCMOS integration of SiGe:C heterojunction bipolar transistors
    • D. Knoll et al., "BiCMOS integration of SiGe:C heterojunction bipolar transistors", BCTM 2002, pp. 162-166.
    • BCTM 2002 , pp. 162-166
    • Knoll, D.1
  • 8
    • 0036503662 scopus 로고    scopus 로고
    • Minimizing thermal resistance and collector-to-substrate capacitance in SiGe BiCMOS on SOI
    • M. Mastrapasqua et al., "Minimizing thermal resistance and collector-to-substrate capacitance in SiGe BiCMOS on SOI", IEEE EDL vol. 23, 145-147, 2002.
    • (2002) IEEE EDL , vol.23 , pp. 145-147
    • Mastrapasqua, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.