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Volumn , Issue , 2004, Pages 185-188

Comparative analysis of serial vs parallel links in NOC

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; DATA TRANSFER; ELECTRIC LOADS; ENERGY DISSIPATION; INTERCONNECTION NETWORKS; LEAKAGE CURRENTS; NETWORK PROTOCOLS; PARALLEL PROCESSING SYSTEMS; SIGNAL INTERFERENCE; TELECOMMUNICATION LINKS;

EID: 21244484285     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (36)

References (21)
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    • Power efficient inter-module communication for digit-serial DSP architectures in deep-submicron technology
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    • Dhaou, I.B.1    Dubrova, E.2    Tenhunen, H.3
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    • Investigation of performance metrics for interconnect stack architectures
    • P. Gupta, A.B. Kahng, Y. Kim, D. Sylvester, "Investigation of Performance Metrics for Interconnect Stack Architectures", SLIP Conference, pp. 23-29, 2004.
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    • Gupta, P.1    Kahng, A.B.2    Kim, Y.3    Sylvester, D.4
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  • 13
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    • Repeater isertion and wire sizing optimization for throughput-centric VLSI global interconnects
    • H. Shah, P. Shiu, B. Bell, M. Aldredge, N. Sopory, J.A. Davis, "Repeater Isertion and Wire Sizing Optimization for Throughput-Centric VLSI Global Interconnects", ICCAD, pp. 280-284, 2002.
    • (2002) ICCAD , pp. 280-284
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    • Effects of global interconnect optimizations on performance estimation of deep submicron designs
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.