Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2000, Pages 167-172

  Venkatesan, Raguraman ^a   Davis, Jeffrey A ^a   Bowman, Keith A ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MACROCELLS; MULTILEVEL INTERCONNECT ARCHITECTURES;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ENERGY DISSIPATION; INTERCONNECTION NETWORKS; TELECOMMUNICATION REPEATERS;

POWER ELECTRONICS;

EID: 0033666750     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)