20 MB/s data rate 2.5 V flash memory with current-controlled field erasing for 1 M cycle endurance

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 40, Issue , 1997, Pages 396-397

  Dallabora, Marco ^a   Villa, Corrado ^a   Caser, Fabio Tassan ^a   Schippers, Stefan ^a   Sali, Mauro ^a   Ortolani, Giuseppe ^a   Geraci, Antonio ^a   Defendi, Marco ^a   Cane, Marcello ^a   Bettini, Luigi ^a   Bartoli, Simone ^a   Cantarelli, Daniele ^a   Bez, Roberto ^a  

^a STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; DATA TRANSFER; ELECTRIC CURRENT REGULATORS; ELECTRIC CURRENTS; ELECTRIC POWER SUPPLIES TO APPARATUS; MICROPROCESSOR CHIPS; OPTOELECTRONIC DEVICES; OXIDE SUPERCONDUCTORS; ROM; THERMAL EFFECTS; USER INTERFACES;

ADDRESS TRANSITION DETECTOR (ATD); BAND TO BAND TUNNEL (BBT); BUILT IN SELF TEST (BIST) TECHNIQUE; CONTENT ADDRESSABLE MEMORY ARRAY (CAMA); CURRENT CONTROLLED FIELD ERASING (CCFE); ERASE ADDRESS REGISTER (EAR); ERASE SECTOR REGISTER (ESR); FOWLER-NORDHEIM (FN) TUNNEL; PROGRAM BYTE REGISTER (PBR);

NONVOLATILE STORAGE;

EID: 0031072546     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)