Modeling of SiGe Power HBT Intermodulation Distortion using HICUM

European Solid-State Device Research Conference

Volumn , Issue , 2003, Pages 311-314

  Sakalas, P ^a,b   Schroter M ^a   Kornau, L ^a   Kraus, W ^c   Herricht, J ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

^b CENTER FOR PHYSICAL SCIENCES AND TECHNOLOGY   (Lithuania)

^c Atmel Germany GmbH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

POWER HBT;

EID: 20344401929     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2003.1256876     Document Type: Conference Paper

References (12)

1. J.-S. Rieh et al., "SiGe HBTs with Cut-off Frequency of 350 GHz", Proc. IEDM'02, 2002, pp.771-774.
2. J. Berntgen et al., "SiGe technology bears fruits", Materials Science & Engineering, B89, 2002, pp. 13-20.
3. K. Honjo, "Applications of HBTs", Solid-Stale Electronics, Vol.38, 1995, pp.1569-1573.
4. J. Pusl et al., "A Silicon Germanium, High Efficiency Power Amplifier Chipset for GSM/DSC-PCS/WCDMA Handset Application", Proc. of 31st Europ. Microw. Conf., CMP Europe Ltd, London, 2001, pp.83-86.
5. A. Raghavan et al, "A 2.4 GHz High efficiency SiGe HBT Power Amplifier with High-Q LTCC Harmonic Suppression Fitter, IEEE MTT-S Digest, 2002, pp.1019-1022.
6. M. Schroter, "Staying current with H1CUM", IEEE Circuits and Devices Magazine, Vol, 18, pp. 16-25, 2002. see also: http://www.iee.et.tu-dresden.de/iee/eb for detailed documentation and code.
7. L. de Vreede, "Advanced modeling of distortion effects in bipolar transistors using the MEXTRAM model", IEEE Journal of Solid-State Circuits, Vol. 31, 1996, pp. 114-121.
8. M. Schroter et al, "Compact modeling of high-frequency distortion in Si integrated bipolar transistors", IEEE Trans. Electron Dev., Vol.47, pp.1529-1539, 2000.
9. G. Malm et al, "Influence of Ge-profile design and saturation effects on SiGe HBT linearity", ESSDERC 2001.
10. E.P. Vandamme et al, "Improved Three-Step De-embedding method to Accurately Account for the Influence of Pad Parasitics in Silicon On-wafer RF Test-Structures", IEEE Trans. Electron Dev., Vol.48, 2001, pp.737-742.
11. M. Schroter et al, "Physics- and Process-based Bipolar Transistor Modeling for Integrated Circuit Design", IEEE Journal of Solid-Slate Circuits, Vol.34, 1999, pp.1136-1149.
12. M. Rickelt et al, "A novel transistor model for simulating avalanche-breakdown effects in Si bipolar circuits", IEEE J. Solid-State Circuits, Vol.37, 2002, pp.1184-1197.