Scaling of data sensing schemes for high speed cache design in sub-0.18 μm technologies

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2000, Pages 226-227

  Zhang, Kevin ^a   Hose, Ken ^a   De, Vivek ^a   Senyk, Borys ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER ARCHITECTURE;

DATA SENSING;

VLSI CIRCUITS;

EID: 0033700305     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)