Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2-GHz low noise amplifier

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 3, 2005, Pages 726-734

  Han, Kwangseok ^a,b   Han, Jeonghu ^a   Gil, Joonho ^a,c   Shin, Hyungcheol ^a,d   Lee, Kwyro ^a   Song, Seong Sik ^a   Kim, Choong Ki ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b SAMSUNG Electronics   (South Korea)

^c RadioPulse Inc   (South Korea)

^d Seoul National University   (South Korea)

Author keywords

Four noise parameters; Induced gate noise; Low noise amplifier; Noise correlation coefficients; RF CMOS; Thermal noise

Indexed keywords

CMOS INTEGRATED CIRCUITS; CORRELATION METHODS; ERROR ANALYSIS; FREQUENCIES; MATHEMATICAL MODELS; MOSFET DEVICES; PARAMETER ESTIMATION; POWER AMPLIFIERS;

FOUR NOISE PARAMETERS; INDUCTED GATE NOISE; LOW NOISE AMPLIFIERS; NOISE CORRELATION COEFFICIENTS; RF CMOS;

THERMAL NOISE;

EID: 16244402353     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.843637     Document Type: Article

References (25)

1. M. Je, I. Kwon, H. Shin, and K. Lee, "MOSFET modeling and parameter extraction for RF-IC's," in CMOS RF Modeling, Characterization and Applications. Singapore: World Scientific, 2002, pp. 67-120.
2. T. Manku, "Microwave CMOS - Device physics and design," IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 277-285, Mar. 1999.
3. C.-H. Chen and M. J. Deen, "Channel noise modeling of deep submicron MOSFET," IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1484-1487, Aug. 2002.
4. A. J. Scholten, H. J. Tromp, L. F. Tiemeijer, R. van Langevelde, R. J. Havens, P. W. H. de Vreede, R. F. M. Roes, P. H. Woerlee, A. H. Montree, and D. B. M. Klaassen, "Accurate thermal noise model for deep-submicron CMOS," in IEDM Tech. Dig., 1999, pp. 155-158.
5. K. Han, H. Shin, and K. Lee, "Thermal noise modeling for short-channel MOSFET's," in Int. Conf. Simulation of Semiconductor Processes and Devices (SISPAD), 2003, pp. 79-82.
6. _, "Analytical drain thermal noise current model valid for deep submicron MOSFETs," IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 261-269, Feb. 2004.
7. G. Knoblinger, "RF noise of deep-submicron MOSFETs: Extraction and modeling," in Proc. 28th Eur. Solid-State Device Research Conf. (ESS-DERC), 1998, pp. 460-462.
8. R. Kraus and G. Knoblinger, "Modeling the gate-related high-frequency and noise characteristics of deep-submicron MOSFETs," in IEEE Custom Integrated Circuits Conf (CICC), 2002, pp. 209-212.
9. A. J. Scholten, L. F. Tiemeijer, R. van Langevelde, R. J. Havens, A. T. A. Zegers-van Duijhoven, and V. C. Venezia, "Noise modeling for RF CMOS circuit simulation," IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 618-632, Mar. 2003.
10. A. van der Ziel, Noise in Solid State Devices and Circuits. New York: Wiley, 1986.
11. Y. P. Tsividis, Operation and Modeling of the MOS Transistor. New York: McGraw-Hill, 1987.
12. J. Han, M. Je, and H. Shin, "A simple and accurate method for extracting substrate resistance of RF MOSFETs," IEEE Electron Device Lett., vol. 23, no. 7, pp. 434-436, Jul. 2002.
13. H. Hillbrand and P. Russer, "An efficient method for computer aided noise analysis of linear amplifier networks," IEEE Trans. Circuits Syst., vol. 23, no. 4, pp. 235-238, Apr. 1976.
14. C. H. Chen and M. J. Deen, "High frequency noise of MOSFETs," Soild-State Electron., vol. 42, no. 11, pp. 2069-2081, Nov. 1998.
15. D. K. Shaeffer and T. H. Lee, "A 1.5-V 1.5-GHz CMOS low-noise amplifier," IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745-759, May 1997.
16. ADS 2002 Manual, Agilent Technology.
17. J. Gil and H. Shin, "A simple wide-band on-chip inductor model for silicon-based RF ICs," IEEE Trans. Microwave Theory Tech., vol. 50, no. 9, pp. 2023-2028, Sep. 2003.
18. S.-S. Song, S.-W. Lee, J. Gil, and H. Shin, "A simple wide-band MIM capacitor model for RF applications and the effect of substrate grounded shields," in Int. Conf. Solid State Devices and Materials (SSDM), Sep. 2003, pp. 438-439.
19. T. W. Kim and K. Lee, "A simple and analytical design approach for input power matched on-chip LNA," J. Semicond. Technol. Sci., vol. 2, no. 1, pp. 19-29, 2002.
20. J.-S. Goo, H.-T. Ahn, D. J. Ladwig, Z. Yu, T. H. Lee, and R. W. Dutton, "A noise optimization technique for integrated low-noise amplifiers," IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 994-1002, Aug. 2002.
21. P. Andreani and H. Sjoland, "Noise optimization of an inductively degenerated CMOS low noise amplifier," IEEE Trans. Circuits Syst. II, vol. 48, pp. 835-841, 2001.
22. J. Gil, K. Han, and H. Shin, "A 13-GHz 4.67-dB NF CMOS low noise amplifier," Electron. Lett., vol. 39, no. 14, pp. 1056-1058, Jul. 2003.
23. G. Baccarani and M. R. Wordeman, "An investigation of steady-state velocity overshoot in silicon," Solid State Electron., vol. 28, no. 4, pp. 407-416, Apr. 1985.
24. K. Hess and C. T. Sah, "Hot electron in short-gate charge-coupled devices," IEEE Trans. Electron Devices, vol. 25, no. 12, pp. 1399-1405, Dec. 1978.
25. K. Han, H. Shin, and K. Lee, "Drain thermal noise modeling for deep submicron N- and P-channel MOSFETs," Solid-State Electron., no. 12, pp. 2255-2262, Dec. 2004.