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Volumn 39, Issue 14, 2003, Pages 1056-1057

13 GHz 4.67 dB NF CMOS low-noise amplifier

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC RESISTANCE; GAIN MEASUREMENT; IMPEDANCE MATCHING (ELECTRIC); INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL TRANSFORMATIONS; SENSITIVITY ANALYSIS; SPURIOUS SIGNAL NOISE;

EID: 0042346241     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20030687     Document Type: Article
Times cited : (26)

References (8)
  • 1
    • 0042533173 scopus 로고    scopus 로고
    • MOSFET modeling and parameter extraction for RF-IC's
    • in Deen, M.J., and Fjeldly, T.A. (Eds); (World Scientific)
    • Je, M., Kwon, I., Shin, H., and Lee, K.: 'MOSFET modeling and parameter extraction for RF-IC's' in Deen, M.J., and Fjeldly, T.A. (Eds); 'CMOS RF modeling, characterization and applications' (World Scientific, 2002), pp. 67-120
    • (2002) CMOS RF Modeling, Characterization and Applications , pp. 67-120
    • Je, M.1    Kwon, I.2    Shin, H.3    Lee, K.4
  • 2
    • 0035456082 scopus 로고    scopus 로고
    • Noise optimization of an inductively degenerated CMOS low noise amplifier
    • Andreani, P., and Sjoland, H.: 'Noise optimization of an inductively degenerated CMOS low noise amplifier', IEEE Trans. Circuits Syst. II, 2001, 48, pp. 835-841
    • (2001) IEEE Trans. Circuits Syst. II , vol.48 , pp. 835-841
    • Andreani, P.1    Sjoland, H.2
  • 3
    • 0043034084 scopus 로고    scopus 로고
    • A simple and analytical design approach for input power matched on-chip CMOS LNA
    • Kim, T.W., and Lee, K.: 'A simple and analytical design approach for input power matched on-chip CMOS LNA', J. Semicond. Technol. Sci., 2002, 2, (1), pp. 19-29
    • (2002) J. Semicond. Technol. Sci. , vol.2 , Issue.1 , pp. 19-29
    • Kim, T.W.1    Lee, K.2
  • 4
    • 0037399003 scopus 로고    scopus 로고
    • Analysis of packaging effects and optimization in inductively degenerated common-emitter low-noise amplifier
    • Sivonen, P., Kangasmaa, S., and Parssinen, A.: 'Analysis of packaging effects and optimization in inductively degenerated common-emitter low-noise amplifier', IEEE Trans. Microw. Theory Tech., 2003, 51, pp. 1220-1226
    • (2003) IEEE Trans. Microw. Theory Tech. , vol.51 , pp. 1220-1226
    • Sivonen, P.1    Kangasmaa, S.2    Parssinen, A.3
  • 6
    • 85043346516 scopus 로고    scopus 로고
    • MOSFET models for SPICE simulation, including BSIM3v3 and BSIM4
    • (John Wiley & Sons)
    • Liu, W.: 'MOSFET models for SPICE simulation, including BSIM3v3 and BSIM4' (John Wiley & Sons, 2001), pp. 356-361
    • (2001) , pp. 356-361
    • Liu, W.1
  • 7
    • 0032075292 scopus 로고    scopus 로고
    • On-chip spiral inductors with patterned ground shields for Si-based RF IC's
    • Yue, C., and Wong, S.: 'On-chip spiral inductors with patterned ground shields for Si-based RF IC's', IEEE J. Solid-State Circuits, 1998, 33, pp. 743-752
    • (1998) IEEE J. Solid-State Circuits , vol.33 , pp. 743-752
    • Yue, C.1    Wong, S.2
  • 8
    • 0036002395 scopus 로고    scopus 로고
    • On-chip helical inductors for RF-ICs
    • Gil, J., and Shin, H.: 'On-chip helical inductors for RF-ICs', J. Korean Phys. Soc., 2002, 40, (1), pp. 49-51
    • (2002) J. Korean Phys. Soc. , vol.40 , Issue.1 , pp. 49-51
    • Gil, J.1    Shin, H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.