PipeRoute: A pipelining-aware router for FPGAs

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2003, Pages 68-77

  Sharma, Akshay ^a   Ebeling, Carl ^a   Hauck, Scott ^a  

^a UNIVERSITY OF WASHINGTON   (United States)

Author keywords

BFS; Minimum spanning tree; Pipelined circuits; Pipelining; PipeRoute; Retimed circuits; Retiming; Routing

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; CONSTRAINT THEORY; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; OPTIMIZATION;

MINIMUM SPANNING TREE; PIPELINED CIRCUITS; PIPELINED ROUTING PROBLEM; ROUTING ALGORITHM;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0037673251     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. V. Betz and J. Rose, "VPR: A New Packing, Placement and Routing Tool for FPGA Research," Seventh International Workshop on Field-Programmable Logic and Applications, pp 213-222, 1997.
2. D. Cronquist, P. Franklin, C. Fisher, M. Figueroa, and C. Ebeling, "Architecture Design of Reconfigurable Pipelined Datapaths," Twentieth Anniversary Conference on Advanced Research in VLSI, pp 23-40, 1999.
3. C. Ebeling, D. Cronquist, P. Franklin, "RaPiD - Reconfigurable Pipelined Datapath", 6th International Workshop on Field-Programmable Logic and Applications, pp 126-135, 1996.
4. C. Leiserson, F. Rose, and J. Saxe, "Optimizing Synchronous Circuitry", Journal of VLSI and Computer Systems, pp 41-67, 1983.
5. C. Leiserson and J. Saxe, "Retiming Synchronous Circuitry", Algorithmica, 6(1):5-35, 1991.
6. L. McMurchie and C. Ebeling, "PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs", ACM Third International Symposium on Field-Programmable Gate Arrays, pp 111-117, 1995.
7. C. Sechen, VLSI Placement and Global Routing Using Simulated Annealing, Kluwer Academic Publishers, Boston, MA: 1988.
8. A. Sharma, "Development of a Place and Route Tool for the RaPiD Architecture", Master's Project, University of Washington, December 2001.
9. A. Sharma, C. Ebeling, S. Hauck, "PipeRoute: A Pipelining-Aware Router for FPGAs", University of Washington, Dept. of EE Technical Report UWEETR-0018, 2002
10. A. Singh, A. Mukherjee, M. Marek-Sadowska, "Interconnect Pipelining in a Throughput-Intensive FPGA Architecture", ACM/SIGDA Ninth International Symposium on Field-Programmable Gate Arrays, pp. 153-160, 2001.
11. D. Singh, S. Brown, "The Case for Registered Routing Switches in Field Programmable Gate Arrays", ACM/SIGDA Ninth International Symposium on Field-Programmable Gate Arrays, pp 161-169, 2001.
12. D. Singh, S. Brown, "Integrated Retiming and Placement for Field Programmable Gate Arrays", Tenth ACM International Symposium on Field-Programmable Gate Arrays, pp 67-76, 2002.
13. W. Tsu, K. Macy, A. Joshi, R. Huang, N. Walker, T. Tung, O. Rowhani, V. George, J. Wawrzynek and A. DeHon, "HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array", ACM Seventh International Symposium on Field-Programmable Gate Arrays, 1999.