Reducing test time with processor reuse in network-on-chip based systems

Proceedings - 17th Symposium on Integrated Cicuits and Systems Design, SBCCI2004

Volumn , Issue , 2004, Pages 111-116

  Amory, Alexandre M ^a   Cota, Érika ^a   Lubaszewski, Marcelo ^b   Moraes, Fernando G ^c  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^b INSTITUTO DE MICROELECTRÓNICA DE SEVILLA   (Spain)

^c PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

Computer aided test (CAT); Core based test; Network on chip; NoC testing; SoC test; Software based test

Indexed keywords

COMPUTER SOFTWARE; EMBEDDED SYSTEMS; ENERGY DISSIPATION; FAULT TOLERANT COMPUTER SYSTEMS; INTERFACES (COMPUTER); PROGRAM PROCESSORS;

COMPUTER-AIDED TEST (CAT); CORE-BASED TEST; NETWORK-ON-CHIP (NOC); NOC TESTING; SOC TEST; SOFTWARE-BASED TEST;

MICROPROCESSOR CHIPS;

EID: 14244261384     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1016568.1016602     Document Type: Conference Paper

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