Reduced latency IEEE floating-point standard adder architectures

Proceedings - Symposium on Computer Arithmetic

Volumn , Issue , 1999, Pages 35-42

  Beaumont Smith, A ^a   Burgess, N ^a   Lefrere, S ^a   Lim, C C ^a  

^a UNIVERSITY OF ADELAIDE   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

FLAGGED PREFIX ADDITION; FLOATING POINT ADDER; REDUCED LATENCY;

ALGORITHMS; CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; PARALLEL PROCESSING SYSTEMS; VLSI CIRCUITS;

ADDERS;

EID: 0032667920     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (21)