How many logic levels does floating-point addition require?

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1998, Pages 142-149

  Seidel, Peter M ^a   Even, Guy ^a  

^a SAARLAND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; FLIP FLOP CIRCUITS; PIPELINE PROCESSING SYSTEMS; STANDARDS;

FLOATING POINT ADDITION; LOGIC LEVELS;

DIGITAL ARITHMETIC;

EID: 0032301099     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)