Dual precision IEEE floating-point multiplier

Integration, the VLSI Journal

Volumn 29, Issue 2, 2000, Pages 167-180

  Even, Guy ^a   Mueller, Silvia M ^b   Seidel, Peter Michael ^c  

^a TEL AVIV UNIVERSITY   (Israel)

^b IBM   (Germany)

^c Southern Methodist University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DIGITAL ARITHMETIC;

FLOATING POINT MULTIPLIER;

MULTIPLYING CIRCUITS;

EID: 0034266126     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9260(00)00006-7     Document Type: Article

References (12)

1. W.S. Briggs, D.W. Matula, A 17× 69 bit multiply and add unit with redundant binary feedback and single cycle latency, Proceedings 11th Symposium on Computer Arithmetic, number 11, 1993, pp. 163-170.
2. Chromatic's Mpact 2 boosts 3D, Microprocessor Rep. 10 (15) (1996) pp. 1, 66-10.
3. J. Fandrianto, B.Y. Woo, VLSI floating-point processors, Proceedings Seventh Symposium on Computer Arithmetic, number 7, 1985, pp. 93-100.
4. C. Gamez, R. Pang, Apparatus and method for rounding operands, U.S. patent 5258943, 1993.
5. C. Hansen, MicroUnity's media processor architecture, IEEE Micro 16 (4) (1996) pp. 34-41.
6. Hitachi SH-4 gets graphically superscalar, Microprocessor Rep. 10 (14) 1996.
7. N. Quach, N. Takagi, M. Flynn, On fast IEEE rounding, Technical Report CSL-TR-91-459, Stanford University, January 1991.
8. M. Saishi, T. Minemaru, Multiplication circuit having rounding function, U.S. patent 5500812, 1996.
9. Samsung launches media processor, Microprocessor Rep. 10 (11) (1996) pp. 1, 6-9.
10. M.R. Santoro, G. Bewick, M.A. Horowitz, Rounding algorithms for IEEE multipliers, Proceedings Ninth Symposium on Computer Arithmetic, 1989, pp. 176-183.
11. R.K. Yu, G.B. Zyner, 167 MHz radix-4 floating point multiplier, Proceedings 12th Symposium on Computer Arithmetic, 1995, pp. 149-154.
12. G. Zyner, Circuitry for rounding in a floating point multiplier, U.S. patent 5150319, 1992.