Floating point adder/subtractor performing IEEE pounding and addition/subtraction in parallel

IEICE Transactions on Information and Systems

Volumn E79-D, Issue 4, 1996, Pages 297-305

  Park, Woo Chan ^a,b   Lee, Shi Wha ^a   Kwon, Oh Young ^a   Han, Tack Don ^a   Kim, Shin Dug ^a  

^a Yonsei University   (South Korea)

^b Samsung Advanced Institute of Technology (SAIT)   (South Korea)

Author keywords

Carry select adder; Floatingpoint adder subtractor; Fpu(floating point unit); Ieee rounding

Indexed keywords

ADDERS; COMPUTER HARDWARE; DIGITAL ARITHMETIC; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; OPTIMIZATION;

CARRY SELECT ADDER; CENTRAL PROCESSING UNIT; FLOATING POINT UNIT;

PARALLEL PROCESSING SYSTEMS;

EID: 0030123161     PISSN: 09168532     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (12)

1. D. Alpert and D. Avnon, "Architecture of the pentium microprocessor," IEEE Micro, vol.13, no.3, pp.11-21, June 1993.
2. D.W. Dobberpuhl, R.T. Witek, R. Allmon, R. Anglin, D. Bertucci, S. Britton, L. Chao, R.A. Conrad, D.E. Dever, B. Gieseke, S.M.N. Hassoun, G.W. Hoeppner, K. Kuchler, M. Ladd, B.M. Leary, L. Madden, E.J. McLellan, D.R. Meyer, J. Montanaro, D.A. Priore, V. Rajagopalan, S. Samudrala, and S. Santhanam, "A 200-MHz 64-bit dualissue CMOS microporcessor," IEEE J. Solid-state Circuits, vol.27, no.ll, pp.1555-1567, Nov. 1992.
3. C.R. Moore, M.C. Becker, M.S. Alien, and O.P. Tuttle "The PowerPC 601 microprocessor," IEEE Micro, vol.13, no.5, pp.54-67, Oct. 1993.
4. L. Kohn and N. Margulis, "Introducing the Intel i860 64bit microprocessor," IEEE Micro, vol.9, no.4, pp. 15-30, Aug. 1989.
5. D. Goldberg, "Computer arithmetic," Appendix A of J.L. Hennessy and D.A. Patterson, Computer architecture: a quantitative approach, Morgan Kaufmann Publishers Inc, 1990.
6. R. K. Montoye, E. Hokenek, and S. L. Runyon, "Design of IBM RISC/6000 floating-point execution unit," IBM J. Res. Develop., vol.34, no.l, pp.59-70, Jan. 1990.
7. M. Awaga and H. Takahashi, "The /jVP 64-bit vector coprocessor: a new implementation of high-performance numerical computation," IEEE Micro, vol.13, no.5, pp.2436, Oct. 1993.
8. IEEE Std 754-1985, "IEEE standard for binary floatingpoint arithmetic," IEEE, 1985.
9. N. Quach and M.J. Flynn, "Design and implementation of the SNAP floating-point adder," CSL-TR-91-501, Stanford University, Dec. 1991.
10. H. Fujii, C. Hori, T. Takada, N. Hatanaka, T. Demura, and G. Ootomo, "A floating-point cell library and a 100MFLOPS image signal processor," IEEE J. Solid-state Circuits, vol.37, no.7, pp.1080-1088, July 1992.
11. S. Vassliladis, D.S. Lemon, and M. Putrino, "S/370 sign-maginitude floating-point adder," IEEE J. Solid-state Circuit, vol.24, no.4, pp.1062-1070, Aug. 1989.
12. M.R. Santoro, G. Bewick, and M.A. Horowitz/'Rounding algorithms for IEEE multiplier," Proc. IEEE 9th Symp. on Comput. Arithmetic, pp.176-183, June 1989.