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Volumn 36, Issue 1-2, 2003, Pages 69-82

Generation of representative input vectors for parametric designs: From low precision to high precision

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; DIGITAL ARITHMETIC; INTEGRATED CIRCUIT LAYOUT; MULTIPLEXING; VECTORS;

EID: 0042514815     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9260(03)00033-6     Document Type: Article
Times cited : (2)

References (13)
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    • Akers, S.1
  • 2
    • 0022769976 scopus 로고
    • Graph-based algorithms for Boolean function manipulation
    • Bryant R. Graph-based algorithms for Boolean function manipulation. IEEE Trans. Comput. C-35:1986;677-691.
    • (1986) IEEE Trans. Comput. , vol.C-35 , pp. 677-691
    • Bryant, R.1
  • 3
    • 0029292183 scopus 로고
    • Comparing layouts with HDL models: A formal verification technique
    • Kam T., Subrahmanyam P.A. Comparing layouts with HDL models: a formal verification technique. IEEE Trans. 14(4):1995;503-509.
    • (1995) IEEE Trans. , vol.14 , Issue.4 , pp. 503-509
    • Kam, T.1    Subrahmanyam, P.A.2
  • 4
    • 0020923381 scopus 로고
    • On the acceleration of test generation algorithms
    • Fujiwara H., Shimono T. On the acceleration of test generation algorithms. IEEE Trans. Comput. C-32(12):1983;1137-1144.
    • (1983) IEEE Trans. Comput. , vol.C-32 , Issue.12 , pp. 1137-1144
    • Fujiwara, H.1    Shimono, T.2
  • 5
    • 0019543877 scopus 로고
    • An implicit enumeration algorithms to generate tests for combinational logic circuits
    • Goel P. An implicit enumeration algorithms to generate tests for combinational logic circuits. IEEE Trans. Comput. C-30:1981;215-222.
    • (1981) IEEE Trans. Comput. , vol.C-30 , pp. 215-222
    • Goel, P.1
  • 7
    • 0026623575 scopus 로고
    • Test pattern generation using Boolean satisfiability
    • Larrabee T. Test pattern generation using Boolean satisfiability. IEEE Trans. 11(1):1992;4-15.
    • (1992) IEEE Trans. , vol.11 , Issue.1 , pp. 4-15
    • Larrabee, T.1
  • 8
    • 0023865139 scopus 로고
    • SOCRATES: A highly efficient automatic test pattern generation system
    • Schulz M.H., Trischler E., Sarfert T.M. SOCRATES: a highly efficient automatic test pattern generation system. IEEE Trans. Comput. 7:1988;126-137.
    • (1988) IEEE Trans. Comput. , vol.7 , pp. 126-137
    • Schulz, M.H.1    Trischler, E.2    Sarfert, T.M.3
  • 9
    • 84911547644 scopus 로고
    • Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits
    • Ruth J., Bouricious W., Schneide P. Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits. IEEE Trans. Comput. EC-16(5):1967;567-580.
    • (1967) IEEE Trans. Comput. , vol.EC-16 , Issue.5 , pp. 567-580
    • Ruth, J.1    Bouricious, W.2    Schneide, P.3
  • 11
    • 0034870484 scopus 로고    scopus 로고
    • On the design of fast IEEE floating-point adders
    • N. Burgess, L. Ciminiera (Eds.)
    • P.-M. Seidel, G. Even, On the design of fast IEEE floating-point adders, in: N. Burgess, L. Ciminiera (Eds.), Computer Arithmetic, Proceedings, 15th IEEE Symposium on, 2001, pp. 184-194 (See also http://hyde.eng.tau.ac.il/Projects/FPADD/index.html for a visualization tool, in which the data flow and control signals are described).
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    • On the design of IEEE compliant floating point units
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    • Even, G.1    Paul, W.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.