A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 2, 2004, Pages 378-383

  Pellerano, S ^a   Levantino, S ^a   Samori, C ^a   Lacaita, A L ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

Dynamic logic; Frequency divider; Frequency synthesizer; HiperLAN; Low power design; Phase noise; Phase locked loops (PLLs); Voltage controlled oscillator (VCO); Wireless LAN

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; FREQUENCY SYNTHESIZERS; LOCAL AREA NETWORKS; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; VARIABLE FREQUENCY OSCILLATORS; WIRELESS TELECOMMUNICATION SYSTEMS;

DYNAMIC LOGIC FREQUENCY DIVIDER; PHASE NOISE; RAIL-TO-RAIL TOPOLOGY; TRUE-SINGLE-PHASE-CLOCK LOGIC;

FREQUENCY DIVIDING CIRCUITS;

EID: 1242288219     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.821784     Document Type: Article

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