Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 3, 1996, Pages 456-465

  Huang, Qiuting ^a,b   Rogenmoser, Robert ^a,b  

^a IEEE

^b ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT MODE; CLOCK FREQUENCY; GIGAHERTZ SINGLE PHASE CLOCKS; SPEED OPTIMIZATION;

ALGORITHMS; APPROXIMATION THEORY; CAPACITANCE; DIGITAL CIRCUITS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; TIMING CIRCUITS; TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 0030107330     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.494209     Document Type: Article

References (16)

1. I. Yuan and C. Svensson, "High-speed CMOS circuit technique," IEEE J. Solid-State Circuits, vol. 24, no. 1, pp. 62-70, Feb. 1989.
2. D. W. Dobberpuhl et al., "A 200-MHz 64-b dual-issue CMOS microprocessor," IEEE J. Solid-State Circuits, vol. 27, no. 11, pp. 1555-1567, Nov. 1992.
3. F. Lu, H. Samueli, J. Yuan, and C. Svensson, "A 700 MHz 24-b pipelined accumulator in 1.2-μm CMOS for application as a numerically controlled oscillator," IEEE J. Solid-State Circuits, vol. 28, no. 8, pp. 878-836, Aug. 1993.
4. J. Yuan and C. Svensson, "Pushing the limits of standard CMOS," IEEE Spectrum, pp. 52-53, Feb. 1991.
5. R. Rogenmoser, N. Felber, Q. Huang, and W. Fichtner, "1.16 GHz dual-modulus 1.2-μm CMOS prescaler," in Proc. IEEE 1993 CICC, San Diego, CA, May 1993, pp. 27.6.1-27.6.4.
6. M. Matson and L. Classer, "Macromodeling and optimization of digital MOS VLSI circuits," IEEE Trans. Computer-Aided Design, vol. CAD-5, no. 4, pp. 659-678, Oct. 1986.
7. Q. Huang, "Speed optimization of edge-triggered nine-transistor D-flip-flops for gigahertz single-phase clocks," in Proc. IEEE 1993 ISCAS, Chicago, IL, May 1993, vol. 3, pp. 2118-2121.
8. M. Shoji, "FET scaling in domino CMOS gates," IEEE J. Solid-State Circuits, vol. SC-20, no. 5, pp. 1067-1071, Oct. 1985.
9. H. Oguey and E. Vittoz, "CODYMOS frequency dividers achieve low power Consumption and high frequency," Electron. Lett., pp. 386-387, Aug. 23, 1973.
10. Q. Huang and R. Rogenmoser, "A glitch-free single-phase DFF for gigahertz applications," in Proc. 1994 IEEE ISCAS, London, May 1994, vol. 4, pp. 11-13.
11. R. Rogenmoser, Q. Huang, and F. Piazza, "1.57 GHz asynchronous and 1.4 GHz dual-modulus 1.2-μm CMOS prescalers," in Proc. IEEE 1994 CICC, San Diego, CA, May 1994, pp. 387-390.
12. M. Bolt, SACISC Blue Book. Zurich: Faselec AG, Mar. 1993.
13. A. A. Abidi, ISSCC Short Course on Wireless Communications. San Francisco, CA: IEEE, Feb. 1994.
14. J. Min, A. Rofougaran, H. Samueli, and A. A. Abidi, "An all-CMOS architecture for a low-power frequency-hopped 900 MHz spread spectrum transceiver," in Proc. IEEE 1994 CICC, San Diego, CA, May 1994, pp. 379-382.
15. M. Thamsirianunt and T. Kwasniewski, "A 1.2 μm CMOS implementation of a low-power 900-MHz mobile radio frequency synthesizer," in Proc. IEEE 1994 CICC, San Diego, CA, May 1994, pp. 383-386.
16. P. Basedau and Q. Huang, "A 1 GHz, 1.5 V monolithic LC oscillator in 1-μm CMOS," in 1994 European Solid-State Circuit Conf. (ESSCIRC), Ulm, Germany, Sept. 1994.