Efficient on-chip communications for data-flow IPs

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2004, Pages 293-303

  Fraboulet, Antoine ^a   Risset, Tanguy ^b  

^a UNIVERSITÉ DE LYON   (France)

^b UNIV LYON   (France)

Author keywords

High level synthesis; Interface generation; SoC simulation; System on chip

Indexed keywords

COMPUTER HARDWARE; COMPUTER SIMULATION; DATA FLOW ANALYSIS; INTERFACES (COMPUTER); INTERNET; NETWORK PROTOCOLS;

HIGH LEVEL SYNTHESIS; INTERFACE GENERATION; SOC SIMULATION; SYSTEM ON CHIP (SOC);

MICROPROCESSOR CHIPS;

EID: 11244291377     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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