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Volumn 1, Issue , 2004, Pages 538-543
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High-level system modeling and architecture exploration with systemC on a network SoC: S3C2510 case study
a
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER ARCHITECTURE;
COMPUTER OPERATING SYSTEMS;
COMPUTER SIMULATION;
FORMAL LOGIC;
INTEGRATED CIRCUIT LAYOUT;
MATHEMATICAL MODELS;
EXHIBITIONS;
SYSTEMS ANALYSIS;
ARCHITECTURE EXPLORATION;
HIGH-LEVEL SYSTEM MODELING;
REGISTER TRANSFER LEVEL (RTL);
TURN AROUND TIME (TAT);
MICROPROCESSOR CHIPS;
LOGIC DESIGN;
ARCHITECTURE EXPLORATION;
HIGH-LEVEL DESIGN;
HIGH-LEVEL SYSTEM MODELS;
ON-CHIP TESTS;
PERFORMANCE DEGRADATION;
PERFORMANCE SIMULATION;
SIMULATION SPEED;
VERIFYING CYCLE;
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EID: 3042522902
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (16)
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References (7)
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