Mapping multirate dataflow to complex RT level hardware models

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 1997, Pages 283-292

  Horstmannshoff, Jens ^a   Groetker, Thorsten ^a   Meyr, Heinrich ^a  

^a RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); COMPUTER HARDWARE; DIGITAL SIGNAL PROCESSING; OPTIMIZATION;

DATA FLOW MODELS;

COMPUTER ARCHITECTURE;

EID: 0030656163     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)