Efficient hardware controller synthesis for synchronous dataflow graph in system level design

Proceedings of the International Symposium on System Synthesis

Volumn 2000-January, Issue , 2000, Pages 79-84

  Jung, Hyunuk ^a   Lee, Kangnyoung ^a   Ha, Soonhoi ^a  

^a Seoul National University   (South Korea)

Author keywords

Automatic control; Computer science; Control system synthesis; Counting circuits; Design methodology; Flow graphs; Hardware design languages; Libraries; Signal synthesis; System level design

Indexed keywords

AUTOMATION; COMPUTER CONTROL SYSTEMS; COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SCIENCE; CONTROL; CONTROL SYSTEM SYNTHESIS; CONTROLLERS; COUNTING CIRCUITS; DATA FLOW ANALYSIS; DATA TRANSFER; DESIGN; DIGITAL SIGNAL PROCESSING; FLOW GRAPHS; GRAPHIC METHODS; HARDWARE; LIBRARIES; SEMANTICS; SIGNAL FLOW GRAPHS; SYNTHESIS (CHEMICAL);

ASYNCHRONOUS INTERACTION; AUTOMATIC HARDWARE SYNTHESIS; DESIGN METHODOLOGY; HARDWARE DESIGN LANGUAGE; SIGNAL SYNTHESIS; SYNCHRONOUS DATA FLOW; SYNCHRONOUS DATAFLOW GRAPHS; SYSTEM LEVEL DESIGN;

DATA FLOW GRAPHS;

EID: 33845942541     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSS.2000.874032     Document Type: Conference Paper

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