Modeling of large-grain polysilicon formation under retardation effect of SPC

IEEE Transactions on Electron Devices

Volumn 51, Issue 12, 2004, Pages 2205-2210

  Cheng, C F ^a   Leung, T C ^a   Poon, M C ^a   Kok, C W ^a   Chan, Mansun ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Crystallization; Large grain; Polysilicon; Thermal annealing; Thin film transistor (TFT)

Indexed keywords

CRYSTAL GROWTH; CRYSTALLIZATION; GRAIN SIZE AND SHAPE; MATHEMATICAL MODELS; RAPID THERMAL ANNEALING; THIN FILM TRANSISTORS;

METAL-INDUCED LATERAL CRYSTALLIZATION; PULSED ANNEALING TECHNIQUE; SOLID PHASE CRYSTALLIZATION;

POLYSILICON;

EID: 10644223609     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.838323     Document Type: Article

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