Diagnostic of path and gate delay faults in non-scan sequential circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1995, Pages 380-386

  Girard, P ^a   Landrault, C ^a   Pravossoudovitch, S ^a   Rodriguez, B ^a  

^a LIRMM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUITS; FAULT DIAGNOSIS; GATE DELAY FAULTS; NONSCAN SEQUENTIAL CIRCUITS; PATH DELAY FAULTS; PATH TRACING;

ALGORITHMS; DEFECTS; EFFICIENCY; FAILURE ANALYSIS; IDENTIFICATION (CONTROL SYSTEMS); INTEGRATED CIRCUIT TESTING; LOGIC GATES; MATHEMATICAL MODELS; STANDARDS;

SEQUENTIAL CIRCUITS;

EID: 0029213270     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)