Low Error Fixed-Width CSD Multiplier with Efficient Sign Extension

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 50, Issue 12, 2003, Pages 984-993

  Kim, Sang Min ^a   Chung, Jin Gyun ^b   Parhi, Keshab K ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

^b Chonbuk National University   (South Korea)

Author keywords

Canonic signed digit (CSD); Error compensation bias; Fixed width multiplier; Quantization

Indexed keywords

COMPUTER HARDWARE; COMPUTER SIMULATION; ERROR COMPENSATION; ESTIMATION; LOGIC GATES; PROBABILITY; SPURIOUS SIGNAL NOISE; VECTORS;

CANONIC SIGNED DIGITS (CSD); FIXED-WIDTH MULTIPLIERS; QUANTIZATION; SIGN EXTENSION REDUCTION METHOD;

MULTIPLYING CIRCUITS;

EID: 0347337991     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSII.2003.820231     Document Type: Article

References (18)

1. N. Yoshida, E. Goto, and S. Ichikawa, "Pseudorandom founding for truncated multipliers," IEEE Trans. Comput., vol. 40, pp. 1065-1067, Sept. 1991.
2. Y. C. Lim, "Single precision multiplier with reduced circuit complexity for signal processing applications," IEEE Trans. Comput., vol. 41, pp. 1333-1336, Oct. 1992.
3. M. J. Schulte and E. E. Swartzlander, Jr., "Truncated multiplication with correction constant," VLSI Signal Processing VI, pp. 388-396, Oct. 1993.
4. S. S. Kidambi, F. El-Guibaly, and A. Antoniou, "Area-efficient multipliers for digital signal processing applications," IEEE Trans. Circuits Syst. II, vol. 43, pp. 90-94, Feb. 1996.
5. E. J. King and E. E. Swartzlander, Jr., "Data-dependent truncation scheme for parallel multipliers," in Proc. 31st Asilomar Conf. Signals, Systems, and Computers, Pacific Grove, CA, 1997, pp. 1178-1182.
6. E. E. Swartzlander, Jr., "Truncated multiplication with approximate rounding," in Proc. 31st Asilomar Conf. Signals, Systems, and Computers, Pacafic Grove, CA, 1999, pp. 1480-1483.
7. J. M. Jou, S. R. Kuang, and R. D. Chen, "Design of low-error fixed-width multiplier for dsp applications," IEEE Trans. Circuits Syst. II, vol. 46, pp. 836-842, 1999.
8. L. D. Van, S. S. Wang, and W. S. Feng, "Design of the lower error fixed-width multiplier and its application," IEEE Trans. Circuits Syst. II, vol. 47, pp. 1112-1118, Oct. 2000.
9. L. D. Van and S. H. Lee, "A generalized methodology for lower-error area-efficient fixed-width multipliers," Proc. IEEE ISCAS, pp. 65-68, May 2002.
10. S. J. Jou and H. H. Wang, "Fixed-width multiplier for DSP application," in Proc. ICCD, Austin, TX, Sept. 2000, pp. 318-322.
11. S. W. Reitwiesner, "Binary arithmetic," Advances in Computers, pp. 231-308, 1966.
12. I. Koren, Computer Arithmetic Algorithms. Englewood Cliffs, NJ: Prentice-Hall, 1993.
13. R. A. Hawley, T. J. Lin, and H. Samueli, "A 300 MHz digital double-sideband to single-sideband converter in 1 μm CMOS," IEEE J. Solid-State Circuits, vol. 30, pp. 4-10, Jan. 1995.
14. S. M. Kim, J. G. Chung, and K. K. Parhi, "Sign extension reduction by propagated-carry selection," in Proc. 35th Asilomar Conf. Signals, Systems, and Computers, Pacafic Grove, CA, Nov. 2001, pp. 134-138.
15. _, "Design of low error CSD fixed-width multiplier," in Proc. 2002 IEEE ISCAS, Scottsddale, AZ, May 2002, pp. I-69-I-72.
16. H. Samueli, "An improved search algorithm for the design of multiplierless FIR filters with power-of-two coefficients," IEEE Trans. Circuits Syst., vol. 36, pp. 1044-1047, July 1989.
17. R. Jain, P. T. Yang, and T. Yoshino, "FIRGEN: A computer-aided design system for high performance FIR filter integrated circuits," IEEE Trans. Signal Processing, vol. 39, no. 7, pp. 1655-1668, 1991.
18. J. Laskowski and H. Samueli, "A 150-MHz 43-tap half-band FIR digital filter in 1.2- μm CMOS generated by silicon complier," in Proc CICC, 1992, pp. 11.4.1-11.4.4.