Fixed-width multiplier for DSP application

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2000, Pages 318-322

  Jou, Shyh Jye ^a   Wang, Hui Hsuan ^a  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DIGITAL SIGNAL PROCESSING; ERROR CORRECTION;

BOOTH MULTIPLIERS; COMPENSATION METHODS; FIXED-WIDTH MULTIPLIERS;

FREQUENCY MULTIPLYING CIRCUITS;

EID: 0033681072     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)